Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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20.2. I2C Controller Block Diagram and System Integration

The I2C controller consists of an internal slave interface, an I2C interface, and FIFO logic to buffer data between the two interfaces. †

The host processor accesses data, control, and status information about the I2C controller through a 32-bit slave interface.

Figure 99. I2C Controller Block Diagram

The I2C controller consists of the following modules and interfaces:

  • Slave interface for control and status register (CSR) accesses and DMA transfers, allowing a master to access the CSRs and the DMA to read or write data directly.
  • Two FIFO buffers for transmit and receive data, which hold the Rx FIFO and Tx FIFO buffer register banks and controllers, along with their status levels. †
  • Shift logic for parallel-to-serial and serial-to-parallel conversion
    • Rx shift – Receives data into the design and extracts it in byte format. †
    • Tx shift – Presents data supplied by CPU for transfer on the I2C bus. †
  • Control logic responsible for implementing the I2C protocol.
  • DMA interface that generates handshaking signals to the DMA controller in order to automate the data transfer without CPU intervention. †
  • Interrupt controller that generates raw interrupts and interrupt flags, allowing them to be set and cleared. †
  • Receive filter for detecting events, such as start and stop conditions, in the bus; for example, start, stop and arbitration lost. †