Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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16.5.12.5. Alternative Boot Operation for eMMC Card Devices

The following figure illustrates the sequence of steps required to perform the alternative boot operation for eMMC card devices. The detailed steps are described following the flow chart.
Figure 60. Flow for eMMC Alternative Boot Operation
  1. The software driver checks:
    • If the eMMC card device supports alternative boot operation (the BOOT_INFO bit is set to 1 in the eMMC card).
    • The BOOT_SIZE_MULT and BOOT_BUS_WIDTH values in the card device to use during the boot process.
  2. The software sets the following bits:
    • Sets masks for interrupts by resetting the appropriate bits to 0 in the intmask register.
    • Sets the int_enable bit of the ctrl register to 1. Other bits in the ctrl register must be set to 0.
      Note: Intel recommends writing 0xFFFFFFFF to the rintsts register and idsts register to clear any pending interrupts before setting the int_enable bit. For internal DMA controller mode, the software driver needs to unmask all the relevant fields in the idinten register.
  3. If the software driver needs to use the internal DMA controller to transfer the boot data received, it must perform the following actions:
    • Set up the descriptors as described in Internal DMA Controller Transmission Sequences and Internal DMA Controller Reception Sequences.
    • Set the use internal DMAC bit (use_internal_dmac) of the ctrl register to 1.
  4. Set the card device frequency to 400 kHz using the clkdiv registers. For more information, refer to Clock Setup. Ensure that the card clock is running.
  5. Wait for a time that ensures that at least 74 card clock cycles have occurred on the card interface.
  6. Set the data_timeout field of the tmout register equal to the card device total access time, NAC.
  7. Set the blksiz register to 0x200 (512 bytes).
  8. Set the bytcnt register to multiples of 128K bytes, as indicated by the BOOT_SIZE_MULT value in the card device.
  9. Set the rx_wmark field in the fifoth register. Typically, the threshold value can be set to 512, which is half the FIFO buffer depth.
  10. Set the cmdarg register to 0xFFFFFFFA.
  11. Initiate the command, by setting the cmd register with the following fields:
    • start_cmd = 1
    • enable_boot = 1
    • expect_boot_ack:
      • If a start‑acknowledge pattern is expected from the card device, set expect_boot_ack to 1.
      • If a start‑acknowledge pattern is not expected from the card device, set expect_boot_ack to 0.
    • card_number = 0
    • data_expected = 1
    • cmd_index = 0
    • Set the remainder of cmd register bits to 0.
  12. If no start‑acknowledge pattern is expected from the card device (expect_boot_ack set to 0) jump to step 15.
  13. Wait for the Command Done interrupt.
  14. This step handles the case where a start‑acknowledge pattern is expected (expect_boot_ack was set to 1 in step 11).
    1. If the Boot ACK Received interrupt is not received from the controller within 50 ms of initiating the command (step 11), the start pattern was not received. The software driver must discontinue the boot process and start with normal discovery.

      If internal DMA controller mode is used for the boot process, the controller performs the following steps after the Boot ACK Received timeout:

      • The DMA descriptor is closed.
      • The ces bit in the idsts register is set to 1, indicating the Boot ACK Received timeout.
      • The ri bit of the idsts register is not set.
    2. If the Boot ACK Received interrupt is received, the software driver must clear this interrupt by writing 1 to it.

      Within 0.95 seconds of the Boot ACK Received interrupt, the Boot Data Start interrupt must be received from the controller. If this does not occur, the software driver must discontinue the boot process and start with normal discovery.

      If internal DMA controller mode is used for the boot process, the controller performs the following steps after the Boot ACK Received timeout:

      • The DMA descriptor is closed.
      • The ces bit in the idsts register is set to 1, indicating Boot Data Start timeout.
      • The ri bit of the idsts register is not set.
    3. If the Boot Data Start interrupt is received, it indicates that the boot data is being received from the card device. When the DMA engine is not in internal DMA controller mode, the software driver can then initiate a data read from the controller based on the rxdr interrupt bit in the rintsts register.

      In internal DMA controller mode, the DMA engine starts transferring the data from the FIFO buffer to the system memory as soon as the level specified in the rx_wmark field of the fifoth register is reached.

    4. The software driver must terminate the boot process by instructing the controller to send the SD/SDIO GO_IDLE_STATE command:
      • Reset the cmdarg register to 0.
      • Set the start_cmd bit of the cmd register to 1, and all other bits to 0.
    5. At the end of a successful boot data transfer from the card, the following interrupts are generated:
      • The cmd bit and dto bit in the rintsts register
      • The ri bit in the idsts register, in internal DMA controller mode only
    6. If an error occurs in the boot ACK pattern (0b010) or an EBE occurs:
      • The controller does not generate a Boot ACK Received interrupt.
      • The controller detects Boot Data Start and generates a Boot Data Start interrupt.
      • The controller continues to receive boot data.
      • The application must abort the boot process after receiving a Boot Data Start interrupt.
    7. In internal DMA controller mode:
      • If the software driver creates more descriptors than required by the received boot data, the extra descriptors are not closed by the controller.
      • If the software driver creates fewer descriptors than required by the received boot data, the controller generates a Descriptor Unavailable interrupt and does not transfer any further data to system memory.
    8. If NAC is violated between data block transfers, a DRTO interrupt is asserted. Apart from this, if there is an error associated with the start or end bit, the SBE or EBE interrupt is also generated.

    The alternative boot operation for eMMC card devices is complete. Do not execute the remaining steps (15 and 16).

  15. Wait for the Command Done interrupt.
  16. This step handles the case where a start‑acknowledge pattern is not expected (expect_boot_ack was set to 0 in step 11).
    1. If the Boot Data Start interrupt is not received from the controller within 1 second of initiating the command (step 11), the software driver must discontinue the boot process and start with normal discovery. In internal DMA controller mode:
      • The DMA descriptor is closed.
      • The ces bit in the idsts register is set to 1, indicating Boot Data Start timeout.
      • The ri bit of the idsts register is not set.
    2. If a Boot Data Start interrupt is received, the boot data is being received from the card device. When the DMA engine is not in internal DMA controller mode, the software driver can then initiate a data read from the controller based on the rxdr interrupt bit in the rintsts register.

      In internal DMA controller mode, the DMA engine starts transferring the data from the FIFO buffer to the system memory as soon as the level specified in the rx_wmark field of the fifoth register is reached.

    3. The software driver must terminate the boot process by instructing the controller to send the SD/SDIO GO_IDLE_STATE (CMD0) command:
      • Reset the cmdarg register to 0.
      • Set the start_cmd bit in the cmd register to 1, and all other bits to 0.
    4. At the end of a successful boot data transfer from the card, the following interrupts are generated:
      • The cmd bit and dto bit in the rintsts register
      • The ri bit in the idsts register, in internal DMA controller mode only
    5. In internal DMA controller mode:
      • If the software driver creates more descriptors than required by the received boot data, the extra descriptors are not closed by the controller.
      • If the software driver creates fewer descriptors than required by the received boot data, the controller generates a Descriptor Unavailable interrupt and does not transfer any further data to system memory.

The alternative boot operation for eMMC card devices is complete.