Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

12.3.1.6. GPIO Interconnect Between the HPS and FPGA

Thirty-two general purpose inputs and thirty-two general purpose outputs are provided to the FPGA and are controlled through registers in the System Manager. No interrupts are generated through the input pins. All inputs are synchronized within the System Manager. Output signals should be synchronized in the fabric.
  • h2f_gp_in [31:0]—Provides a low-latency, low-performance, and simple way to read general-purpose signals driven from the fabric. If the FPGA is not in User Mode, the value of this field is undefined.
  • h2f_gp_out [31:0]—Provides a low-latency, low-performance, and simple way to drive general-purpose signals to the fabric. When read returns the current value being driven to the fabric.