Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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8.3.2.2. Peripheral Request Interface Mapping

You can assign a peripheral request interface to any of the DMA channels.

The DMAC supports 32 peripheral request interfaces. Each request interface can receive up to one outstanding request and is assigned a specific peripheral device ID. The following table lists the peripheral device ID assignments.
Table 84.  Peripheral Request Interface Mapping

Peripheral

Request Interface ID

FPGA 0

0

FPGA 1

1

FPGA 2

2

FPGA 3

3

FPGA 4

4

FPGA 5

5

FPGA 6/I2C EMAC2 Tx 12

6

FPGA 7/I2C EMAC2 Rx12

7

I2C0 Tx

8

I2C0 Rx

9

I2C1 Tx

10

I2C1 Rx

11

I2C EMAC0 Tx

12

I2C EMAC0 Rx

13

I2C EMAC1 Tx

14

I2C EMAC1 Rx

15

SPI0 Master Tx

16

SPI0 Master Rx

17

SPI0 Slave Tx

18

SPI0 Slave Rx

19

SPI1 Master Tx

20

SPI1 Master Rx

21

SPI1 Slave Tx

22

SPI1 Slave Rx

23

Reserved

24

Reserved

25

STM

26

Reserved

27

UART0 Tx

28

UART0 Rx

29

UART1 Tx

30

UART1 Rx

31

12 These interfaces are MUXed and controlled by software; since the HPS requires a total of 33 peripheral request interfaces and the DMAC supports a maximum of 32 interfaces.