Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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16.4.3.2.2. Data Receive

The data‑receive state machine receives data two clock cycles after the end bit of a data read command, even if the command path detects a response error or response CRC error. If a response is not received from the card because a response timeout occurs, the BIU does not receive a signal that the data transfer is complete. This happens if the command sent by the controller is an illegal operation for the card, which keeps the card from starting a read data transfer.

If data is not received before the data timeout, the data path signals a data timeout to the BIU and an end to the data transfer done. Based on the value of the transfer_mode bit in the cmd register, the data‑receive state machine gets data from the card data bus in a stream or block(s).

Figure 49. Data Receive State Machine

Stream Data Read

A stream‑read data transfer occurs if the transfer_mode bit in the cmd register is set to 1, at which time the data path receives data from the card and writes it to the FIFO buffer. If the FIFO buffer becomes full, the card clock stops and restarts once the FIFO buffer is no longer full.

An open‑ended stream‑read data transfer occurs if the bytcnt register is set to 0. During this type of data transfer, the data path continuously receives data in a stream until the host software issues an SD/SDIO STOP command. A stream data transfer terminates two clock cycles after the end bit of the STOP command.

If the bytcnt register contains a nonzero value and the send_auto_stop bit in the cmd register is set to 1, a STOP command is internally generated and loaded into the command path, where the end bit of the STOP command occurs after the last byte of the stream data transfer is received. This data transfer can terminate if the host issues an SD/SDIO STOP or STOP_TRANSMISSION (CMD12) command before all the data bytes are received from the card.

Single-block Data Read

If the ctype register is set to a 1‑bit, 4‑bit, or 8‑bit data transfer, data is received from 1, 4, or 8 data lines, respectively, and CRC‑16 is separately generated and checked for 1, 4, or 8 data lines, respectively. If there is a CRC‑16 mismatch, the data path signals a data CRC error to the BIU. If the received end bit is not 1, the BIU receives an End-bit Error (EBE).

Multiple-block Data Read

If the transfer_mode bit in the cmd register is clear and the value of the bytcnt register is not equal to the value of the block_size register, the transfer is a multiple‑block read‑data transfer. The data‑receive state machine receives data in blocks, where the number of bytes in a block is equal to the block size, including the internally‑generated CRC‑16.

If the ctype register is set to a 1‑bit, 4‑bit, or 8‑bit data transfer, data is received from 1, 4, or 8 data lines, respectively, and CRC‑16 is separately generated and checked for 1, 4, or 8 data lines, respectively. After a data block is received, if the remaining byte count becomes zero, the data path signals a data transfer to the BIU.

If the remaining data bytes are greater than zero, the data path state machine causes another data block to be received. If CRC‑16 of a received data block does not match the internally‑generated CRC‑16, a data CRC error is sent to the BIU and the data transmission continues until all bytes are transmitted. Additionally, if the end of a received data block is not 1, data on the data path signals terminate the bit error to the CIU and the data‑receive state machine terminates data reception, waits for data timeout, and signals to the BIU that the data transfer is complete.

If the send_auto_stop bit in the cmd register is set to 1, the SD/SDIO STOP command is internally generated when the last data block is transferred, where no extra bytes are transferred from the card. The end bit of the STOP command might not exactly match the end bit of the last data block.

If the requested block size for data transfers is less than 4, 16, or 32 bytes for 1‑bit, 4‑bit, or 8‑bit data transfer modes, respectively, the data‑transmit state machine terminates the data transfer when all data is transferred, at which point the internally‑generated STOP command is loaded in the command path. Data received from the card after that are then ignored by the data path.

If the bytcnt register is 0 (the block size must be greater than zero), the transfer is an open‑ended block transfer. For this type of data transfer, the data‑receive state machine continues the block‑read data transfer until the host software issues an SD/SDIO STOP or STOP_TRANSMISSION (CMD12) command.