Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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15.3. NAND Flash Controller Signal Descriptions

All NAND pins have to be from one of the following categories:
  • HPS I/O
  • FPGA I/O
The following table lists all NAND Flash pin options available to both the HPS and FPGA.
Table 104.  NAND Flash Pin Options
Pins Supported Data Width Supported Number of CE and R/B
HPS Pins 8-bit or 16-bit 1
FPGA Pins 8-bit or 16-bit 1 – 4
If you are required to connect multiple NAND devices, you must route the NAND interface to FPGA logic. If you use HPS pins, you can only use one CE and R/B pair. If you use FPGA pins, you can use multiple CE and R/B pairs.
Note: The options are mutually exclusive, which means you cannot use HPS pins, and route the CE and R/B signals to FPGA pins.
Table 105.  NAND Flash Controller Interface Signals (Routed to HPS I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
NAND_ADQ[15:0] 16 Input / Output Data Signals. 16'b1111111111111111 Pull-up
NAND_ALE 1 Output Address Latch Enable. When ALE is high, addresses are latched into the NAND address register on the rising edge of the WE_N signal. Pull-up
NAND_CE_N 1 Output Chip Enable. If CE_N is not asserted, the NAND device remains in standby mode and not respond to any control signals. Pull-up
NAND_CLE 1 Output Command Latch Enable. When CLE is high, commands are latched into the NAND command register on the rising edge of the WE_N signal. Pull-up
NAND_RE_N 1 Output Read Enable. RE_N enables the output data buffers. Pull-up
NAND_RB 1 Input Ready/Busy. If the NAND device is busy, the RB signal is asserted low. This signal is open drain and needs a pull-up resistor. 1'b1 Pull-up
NAND_WE_N 1 Output Write Enable. WE_N is responsible for clocking data, address, or commands into the NAND. Pull-up
NAND_WP_N 1 Output Write Protect. Pull-up
Table 106.  NAND Flash Controller Interface Signals (Routed to FPGA I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
nand_adq_i[15:0] 16 Input Data Signals (input). 16'b1111111111111111 Pull-up
nand_adq_oe 1 Output Data Signals (output enable). Pull-up
nand_adq_o[15:0] 16 Output Data Signals (output). Pull-up
nand_ale_o 1 Output Address Latch Enable. When ALE is high, addresses are latched into the NAND address register on the rising edge of the WE_N signal. Pull-up
nand_ce_n_o[3:0] 4 Output Chip Enable. If CE_N is not asserted, the NAND device remains in standby mode and not respond to any control signals. Pull-up
nand_cle_o 1 Output Command Latch Enable. When CLE is high, commands are latched into the NAND command register on the rising edge of the WE_N signal. Pull-up
nand_re_n_o 1 Output Read Enable. RE_N enables the output data buffers. Pull-up
nand_rdy_busy_i[3:0] 4 Input Ready/Busy. If the NAND device is busy, the RB signal is asserted low. This signal is open drain and needs a pull-up resistor. 4'b1111 Pull-up
nand_we_n_o 1 Output Write Enable. WE_N is responsible for clocking data, address, or commands into the NAND. Pull-up
nand_wp_n_o 1 Output Write Protect. Pull-up
s2f_nand_irq 1 Output Interrupt Pull-up