Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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19.3.2. FPGA Routing

Two sets of SPI Master and two sets of SPI Slave Pins are available for routing to the FPGA . The signal names are shown below.

Table 198.  SPI Master Signals (Routed to FPGA I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
spim<1:0>_mosi_o 1 Output Transmit data line for the SPI master
spim<1:0>_miso_i 1 Input Receive data line for the SPI master 1'b1 Pull-up
spim<1:0>_ss_in_n 1 Input Master Contention Input Protocol ss_in_nValue Effect on Serial Transfer
Motorola SPI 1 Enabled
0 Disabled
National Semiconductor Microwire 1 Enabled
0 Disabled
Texas Instruments Serial Protocol (SSP) 1 Disabled
0 Enabled
spim<1:0>_mosi_oe 1 Output Output enable for the SPI master Pull-up
spim<1:0>_ss0_n_o 1 Output Slave Select 0: Slave select signal from SPI master Pull-up
spim<1:0>_ss1_n_o 1 Output Slave Select 1: Allows second slave to be connected to this master Pull-up
spim<1:0>_ss2_n_o 1 Output Slave Select 2: Allows third slave to be connected to this master Pull-up
spim<1:0>_ss3_n_o 1 Output Slave Select 3: Allows fourth slave to be connected to this master Pull-up
spim<1:0>_sclk_out 1 Output Serial clock output Pull-up
s2f_spim<1:0>_irq 1 Output interrupt Pull-down
Table 199.  SPI Slave Signals (Routed to FPGA I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
spis<1:0>_miso_o 1 Output Transmit data line for the SPI Slave
spis<1:0>_mosi_i 1 Input Receive data line for the SPI Slave 1'b1 Pull-up
spis<1:0>_ss_in_n 1 Input Master Contention Input Protocol ss_in_nValue Effect on Serial Transfer
Motorola SPI 1 Enabled
0 Disabled
National Semiconductor Microwire 1 Enabled
0 Disabled
Texas Instruments Serial Protocol (SSP) 1 Disabled
0 Enabled
spis<1:0>_miso_oe 1 Output Output enable for the SPI slave Pull-up
spis<1:0>_clk 1 Input Serial clock output 1'b1 Pull-up
s2f_spis<1:0>_irq 1 Output interrupt Pull-down