Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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6.4.4. Example (Recommended) System Memory Mapping Scheme

When using ECC, the FPGA (through FPGA-to-HPS ) memory map and the MPU memory map must match. During ECC calculations, all internal address bits are used, therefore, in order to prevent ECC Double Bit Error (DBE), the entire address used to access DDR memory must be the same for any master of that memory. Intel highly recommends using the following memory map, which is consistent for all memory spans.
Table 63.  Example (Recommended) Memory Map Table
Total DDR size External DDR address range Address range for MPU Address range for FPGA (FPGA-to-HPS)
2 GB 0x00_0000_0000 – 0x00_7FFF_FFFF 0x00_0000_0000 – 0x00_7FFF_FFFF 0x00_0000_0000 – 0x00_7FFF_FFFF
4 GB 0x00_0000_0000 – 0x00_7FFF_FFFF 0x00_0000_0000 – 0x00_7FFF_FFFF 0x00_0000_0000 – 0x00_7FFF_FFFF
0x00_8000_0000 – 0x00_FFFF_FFFF 0x10_8000_0000 – 0x10_FFFF_FFFF 0x10_8000_0000 – 0x10_FFFF_FFFF
8 GB 0x00_0000_0000 – 0x00_7FFF_FFFF 0x00_0000_0000 – 0x00_7FFF_FFFF 0x00_0000_0000 – 0x00_7FFF_FFFF
0x00_8000_0000 – 0x01_FFFF_FFFF 0x10_8000_0000 – 0x11_FFFF_FFFF 0x10_8000_0000 – 0x11_FFFF_FFFF
16 GB 0x00_0000_0000 – 0x00_7FFF_FFFF 0x00_0000_0000 – 0x00_7FFF_FFFF 0x00_0000_0000 – 0x00_7FFF_FFFF
0x00_8000_0000 – 0x03_FFFF_FFFF 0x10_8000_0000 – 0x13_FFFF_FFFF 0x10_8000_0000 – 0x13_FFFF_FFFF
32 GB 0x00_0000_0000 – 0x00_7FFF_FFFF 0x00_0000_0000 – 0x00_7FFF_FFFF 0x00_0000_0000 – 0x00_7FFF_FFFF
0x00_8000_0000 – 0x07_FFFF_FFFF 0x10_8000_0000 – 0x17_FFFF_FFFF 0x10_8000_0000 – 0x17_FFFF_FFFF
64 GB 0x00_0000_0000 – 0x00_7FFF_FFFF 0x00_0000_0000 – 0x00_7FFF_FFFF 0x00_0000_0000 – 0x00_7FFF_FFFF
0x00_8000_0000 – 0x0F_FFFF_FFFF 0x10_8000_0000 – 0x1F_FFFF_FFFF 0x10_8000_0000 – 0x1F_FFFF_FFFF