Article ID: 000090809 Content Type: Troubleshooting Last Reviewed: 06/21/2022

How to configure FPGA-to-SDRAM interface when ECC is turned on in Intel® Stratix® 10 SX devices?



When error correction code (ECC) is turned on in the HPS External Memory Interface (EMIF) in Intel® Stratix® 10 SX device, the memory address generates ECC data for F2H and F2SDRAM0/1/2 interfaces. FPGA-to-HPS masters are required to use the same memory address with MPU even when using F2SDRAM0/1/2 interfaces. Otherwise, an ECC error might be triggered. This restriction does not apply when ECC is turned off.


When the FPGA-to-HPS master and MPU master get access to the memory space lower than 2 GB, the memory address is used from 0x0000 0000 to 0x7FFF FFFF.

When the FPGA-to-HPS master and MPU master get access to the memory space larger than 2 GB, MPU uses the alias address defined in the DTS file to access these memory addresses. The FPGA-to-HPS master must use the same alias address instead of the physical address for all F2SDRAM0/1/2 interfaces.

Here is the example of 4 GB HPS EMIF in an Intel® Stratix® 10 SX device:

In DTS, memory is defined into two regions, as shown below. Then FPGA-to-HPS master and MPU must use address from 0x1080000000 to 0x10FFFFFFFF to access the 2 GB ~ 4 GB memory space.

memory {

  reg = <0 0x00000000 0 0x80000000>,

            <0x10 0x80000000 0 0x80000000>;


To enable  access to the full 4 GB memory space with the alias address shown above, the following F2SDRAM firewall registers should also be set accordingly:

#Example, F2SDRAM0 region0 config, you can configure them in U-Boot source, i.e. uboot-socfpga\arch\arm\mach-socfpga\spl_s10.c

writel(0x1000000, 0xF8020210); // region0addr_base
writel(0x0, 0xF8020214); // region0addr_baseext
writel(0xFFFFFFFF, 0xF8020218); // region0addr_limit (lower 32bits)
writel(0x10, 0xF802021C); //region0addr_limitext (upper 32bits)
writel(0x1, 0xF8020204); //enable_set for regions



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Intel® Stratix® 10 FPGAs and SoC FPGAs



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