Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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19.3.1. Interface to HPS I/O

Two sets of SPI Master and two sets of SPI Slave Pins are available to the HPS I/O. The pin names are shown below.

Table 196.   Structured ASIC SPI Master Signals (Routed to HPS I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
SPIM<1:0>_CLK 1 Output Serial clock output from the SPI master Pull-up
SPIM<1:0>_MOSI 1 Output Transmit data line for the SPI master
SPIM<1:0>_MISO 1 Input Receive data line for the SPI master 1'b1 Pull-up
SPIM<1:0>_SS0_N 1 Output Slave Select 0: Slave select signal from SPI master Pull-up
SPIM<1:0>_SS1_N 1 Output Slave Select 1: Slave select signal from SPI master Pull-up
Table 197.   Structured ASIC SPI Slave Signals (Routed to HPS I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
SPIS<1:0>_CLK 1 Input Serial clock input to the SPI slave 1'b1 Pull-up
SPIS<1:0>_MOSI 1 Input Receive data line for the SPI slave 1'b1 Pull-up
SPIS<1:0>_MISO 1 Output Transmit data line for the SPI slave
SPIS<1:0>_SS0_N 1 Input Slave select input to the SPI slave 1'b1 Pull-up