Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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7.3. FPGA-to-HPS Bridge

The FPGA-to-HPS bridge provides access to the peripherals in the HPS from the FPGA. This access is available to any master implemented in the FPGA fabric. You can configure the bridge slave, which is exposed to the FPGA fabric, to support the ACE-Lite protocol, with a data width of 128/256/512 bits.

The FPGA-to-HPS bridge is configurable in the HPS component parameter editor, available in Platform Designer and the IP Catalog. The FPGA master selects either CCU or SDRAM as the target of the transaction by using a user bit on the AXI bus or selecting the interface target in Platform Designer. For more information, refer to the Intel Agilex Hard Processor System Component Reference Manual.

Table 66.   FPGA-to-HPS Bridge PropertiesThe following table lists the properties of the FPGA-to-HPS bridge, including the configurable slave interface exposed to the FPGA fabric.
Bridge Property Value

Data width7

128, 256, or 512 bits

Clock domain

f2h_axi_clock (max 400 MHz)

Address width

40 bits

ID width

5 bits

Read acceptance

16 transactions

Write acceptance

16 transactions

Total acceptance

16 transactions

Note: If the FPGA Fabric Bypass Mux is enabled, then
  • FPGA-to-HPS bridge is not available for FPGA to CCU and FPGA-to-SDRAM traffic.
  • MPFE remains in reset.
  • SDRAM ECC is not available. But, SDRAM traffic can still be ECC protected using the soft logic
  • FPGA-to-SDRAM access is managed in a similar manner like any other IO96 or IO96 pair from the FPGA.
  • SoC to SDRAM path is routed through HPS-to-FPGA port to FPGA. It allows FPGA to control the SDRAM bandwidth allocation as well as in-line encryption for SDRAM traffic.
7 The bridge master data width is user-configurable at the time you instantiate the HPS component in your system.