Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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19.5.6.2.2. Example 2: Transmit FIFO Watermark Level = 192

Consider the example where the assumption is made: †

DMA burst length = FIFO_DEPTH - DMATDLR

Here the number of data items to be transferred in a DMA burst is equal to the empty space in the transmit FIFO buffer. Consider the following:

  • Transmit FIFO watermark level = DMATDLR = 192 †
  • DMA burst length = FIFO_DEPTH - DMATDLR = 64 †
  • SPI transmit FIFO_DEPTH = 256 †
  • Block transaction size = 960 †
Figure 97. Transmit FIFO Watermark Level = 192

Number of burst transactions in block: †

Block transaction size/DMA burst length = 960/64 = 15 †

In this block transfer, there are 15 destination burst transactions in a DMA block transfer. But the watermark level, DMATDLR, is high. Therefore, the probability of SPI transmit underflow is low because the DMA controller has plenty of time to service the destination burst transaction request before the SPI transmit FIFO buffer becomes empty. †

This case has a lower probability of underflow at the expense of more burst transactions per block. This provides a potentially greater amount of bursts per block and worse bus utilization than the former case.