Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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17.4.2. FPGA Routing

Three Ethernet Media Access Controllers are provided in the HPS. The table below describes the signals that are available from each Ethernet Media Access Controller to the FPGA I/O. For more information, refer to the HPS I/O table for general clock to data relationships across the modes.

Table 165.  EMAC Controller Interface Signals (Routed to FPGA I/O)
Signal Name Width Direction Description Default Value for Inputs Recommended Tie-off
emac<2:0>_phy_txclk_i 1 Input

This is the transmit clock (2.5 MHz/25 MHz) provided by the PHY in 10/100 Mbps modes. This clock is not used in GMII mode.

Note: This clock must be able to perform glitch free switching between 2.5 and 25 MHz.
1'b1 Pull-up
emac<2:0>_phy_txclk_o 1 Output

In GMII mode, this signal is the transmit clock output to the PHY to sample data.

For MII, this clock is not used by the PHY, however the transmit clock input from the PHY in 10/100Mbps modes of operation (input on emac_clk_tx_i) is muxed onto this clock output and must be used for the synchronous clock by any adaptation logic on the transmit data and control path in the FPGA fabric for GMII and MII modes.

emac<2:0>_phy_txd_o[7:0] 8 Output

These are a group of eight transmit data signals driven by the EMAC.

All eight bits provide the GMII transmit data byte. For the lower speed MII 10/100 Mbps modes of operation, only bits[3:0] are used. The validity of the data is qualified with phy_txen_o and phy_txer_o. Synchronous to phy_txclk_o.

emac<2:0>_phy_txen_o 1 Output This signal is driven by the EMAC and is used in GMII mode. When driven high, this signal indicates that valid data is being transmitted on the phy_txd_o bus.
emac<2:0>_phy_txer_o 1 Output This signal is driven by the EMAC and when high, indicates a transmit error or carrier extension on the phy_txd_o bus. It is also used to signal low power states in the Energy Efficient Ethernet operation.
emac<2:0>_rst_clk_tx_n_o 1 Output

Transmit clock reset output to the FPGA, which is the internal synchronized reset to phy_txclk_o output from the EMAC. May be used by logic implemented in the FPGA as desired.

The reset pulse width of the rst_clk_tx_n_o signal is three transmit clock cycles.

emac<2:0>_phy_rxclk_i 1 Input

Receive clock from external PHY. For GMII, the clock frequency is 125 MHz. For MII, the receive clock is 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps.

1'b1 Pull-up
emac<2:0>_phy_rxd_i[7:0] 8 Input This is an eight-bit receive data bus from the PHY. In GMII mode, all eight bits are sampled. The validity of the data is qualified with phy_rxdv_i and phy_rxer_i. For lower speed MII operation, only bits [3:0] are sampled. These signals are synchronous to clk_rx_i. 8'b11111111 Pull-up
emac<2:0>_phy_rxdv_i 1 Input

This signal is driven by PHY. In GMII mode, when driven high, it indicates that the data on the phy_rxd_i bus is valid. It remains asserted continuously from the first recovered byte of the frame through the final recovered byte.

1'b0 Pull-down
emac<2:0>_phy_rxer_i 1 Input This signal indicates an error or carrier extension (GMII) in the received frame. This signal is synchronous to clk_rx_i. 1'b1 Pull-up
emac<2:0>_rst_clk_rx_n_o 1 Output Receive clock reset output, synchronous to clk_rx_i. The reset pulse width of the rst_clk_rx_n_o signal is three transmit clock cycles.
emac<2:0>_phy_crs_i 1 Input This signal is asserted by the PHY when either the transmit or receive medium is not idle. The PHY de-asserts this signal when both transmit and receive interfaces are idle. This signal is not synchronous to any clock. 1'b0 Pull-down
emac<2:0>_phy_col_i 1 Input This signal, valid only when operating in half duplex, is asserted by the PHY when a collision is detected on the medium. This signal is not synchronous to any clock. 1'b0 Pull-down
emac<2:0>_phy_mac_speed_o[1:0] 2 Output
emac<2:0>_phy_txd_gmii_o[7:0] 8 Output
s2f_emac<2:0>_irq 1 Output Interrupt
s2f_i2c_emac<2:0>_irq 1 Output Interrupt