Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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25.4.3. System Trace Macrocell

The STM allows messages to be injected into the trace stream for delivery to the host debugger receiving the trace data. These messages can be sent through stimulus ports or the hardware EVENT interface. The STM allows these messages to be time stamped.

The STM supports an EVENT interface that can be used to post additional messages into a trace stream. In addition to the channels, 44 of the 64 EVENT signals are attached to the FPGA, which allows the FPGA to send additional messages using the STM.

The STM has access to one 16 MB region starting at 0xFC000000. The hardware has fixed master IDs for the following masters that have access to this address range::
  • DMA — 0x20
  • FPGA ACE — 0x04
  • CPU3 — 0x03
  • CPU2 — 0x02
  • CPU1 — 0x01
  • CPU0 — 0x00

For more information, refer to the CoreSight System Trace Macrocell Technical Reference Manual on the ARM® Infocenter website.