Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

21.5.2.1. IIR_FCR.TET = 1

IIR_FCR.TET = 1 decodes to a watermark level of 16.

  • Transmit FIFO watermark level = decoded watermark level of IIR_FCR.TET = 16 †
  • DMA burst length = FIFO_DEPTH - decoded watermark level of IIR_FCR.TET = 112 †
  • UART transmit FIFO_DEPTH = 128 †
  • Block transaction size = 448†
Figure 121. Transmit FIFO Watermark Level = 16

The number of burst transactions needed equals the block size divided by the number of data items per burst:

Block transaction size/DMA burst length = 448/112 = 4

The number of burst transactions in the DMA block transfer is 4. But the watermark level, decoded level of IIR_FCR.TET, is quite low. Therefore, the probability of transmit underflow is high where the UART serial transmit line needs to transmit data, but there is no data left in the transmit FIFO. This occurs because the DMA has not had time to service the DMA request before the FIFO becomes empty.