Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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15.5.1.1. NAND Flash Controller Optimization Sequence

The software must configure the flash device for interrupt or polling mode, using the bank0 bit of the rb_pin_enabled register in the config group. If the device is in polling mode, the software must also program the additional registers, to select the times and frequencies of the polling. Program the following registers in the config group:
  • Set the rb_pin_enabled register to the desired mode of operation for each flash device.
  • For polling mode, set the load_wait_cnt register to the appropriate value depending on the speed of operation of the NAND flash controller, and the desired wait value.
  • For polling mode, set the program_wait_cnt register to the appropriate value by software depending on the speed of operation of the NAND flash controller, and the desired wait value.
  • For polling mode, set the erase_wait_cnt register to the appropriate value by software depending on the speed of operation of the NAND flash controller, and the desired wait value.
  • For polling mode, set the int_mon_cyccnt register to the appropriate value by software depending on the speed of operation of the NAND flash controller, and the desired wait value.

At any time, the software can change any flash device from interrupt mode to polling mode or vice‑versa, using the bank0 bit of the rb_pin_enabled register.

The software must ensure that the particular flash device does not have any outstanding transactions before changing the mode of operation for that particular flash device.