Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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17.4. EMAC Controller Signal Description

The EMAC provides a variety of PHY interfaces and control options through the HPS and the FPGA I/Os.

For designs that are pin-limited on HPS I/O, the EMAC can be configured to expose either a GMII or MII PHY interface to the FPGA fabric, which can be routed directly to FPGA I/O pins. Exposing the PHY interface to the FPGA fabric also allows adapting the GMII/MII to other PHY interface types such as SGMII and RMII using soft logic with the appropriate general purpose or transceiver I/O resources.

The figure below depicts a design which routes the EMAC0 and EMAC1 PHY interfaces through the FPGA fabric to provide an RMII and SGMII interface using FPGA I/O. EMAC2's PHY interface has been configured to use the HPS I/O.

Refer to the "EMAC FPGA Interface Initialization" section to find out more information about configuring EMAC interfaces through FPGA.

Figure 63. EMAC to FPGA Routing Example