Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

14.3.1. I/O Pins

The HPS has 48 dedicated I/O pins. They are divided into four quadrants of 12 signals per quadrant.

You can alternatively route most HPS peripherals (except USB) through the FPGA. Select this routing when you instantiate the HPS Component. For more information, refer to the Intel® Agilex™ HPS Component Reference Manual.

Note: When assigning an HPS peripheral to HPS dedicated pins, you must assign all peripheral I/O pins to the same quadrant, except for NANDx16, Trace, and GPIO.
Note: Although the HPS dedicated I/O pins are configured through the control registers, software cannot reconfigure the pins after I/O configuration is complete. There is no support for dynamically changing the pin MUX selections for HPS dedicated I/O pins.