Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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9.3.5.1. Pipeline and Timing

The RAM controller is a pipelined design, where:
  • The Write path (full width) pipeline is two stages deep; therefore providing a two clock latency.
  • The Write path (subword access) pipeline is three stages deep to account for the read-modify-write.
  • The Read path pipeline is four stages deep for RAM.