Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.4.1. L3 Address Space

The L3 address space is 1 TB with the SMMU enabled. This address space applies to all L3 masters.

All L3 address space configurations have the following characteristics:

  • The peripheral region matches the peripheral region in the MPU address space, except that MPU private registers (SCU and L2) and the GIC are inaccessible.
  • The FPGA slaves region is the same as the FPGA slaves region in the MPU address space.
  • The DDR Memory region is the same as the memory region in the MPU address space

The L3 address space configurations contain the regions shown in the following figure:

Figure 16. L3 Address Regions

Internal MPU registers (SCU and L2) are not accessible to L3 masters.

Cache coherent memory accesses have the same view of memory as the MPU.

SDRAM Window Regions

The L3 address map includes two SDRAM window regions when the FPGA-to-HPS traffic is routed via CCU, a 2-GB window and a 124-GB window. Otherwise, when routed directly to SDRAM, the entire 128GB address space is visible.
Figure 17. SDRAM Regions

HPS-to-FPGA Slaves Region

The HPS-to-FPGA slaves region provides access to 4 GB of slaves in the FPGA fabric through the HPS-to-FPGA bridge.

Lightweight HPS-to-FPGA Slaves Region

The lightweight HPS-to-FPGA slaves region provide access to slaves in the FPGA fabric through the lightweight HPS-to-FPGA bridge.

Peripherals Region

The peripherals region includes slaves connected to the L3 interconnect and L4 buses.

On-Chip RAM Region

The on-chip RAM region provides access to on-chip RAM. Although the on-chip RAM region is 1 MB, the physical on-chip RAM is only 256 KB.