Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
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37.3.1. Video Frame Reader IP Interfaces

Table 701.  Video Frame Reader IP Interfaces
Name Direction Width Description
Clocks and resets
main_clock_clk In 1 AXI4-S processing clock.
main_reset_rst In 1 AXI4-S processing reset.
control_clock_clk In 1 Optional control agent interface clock.
control_reset_reset In 1 Optional control agent interface reset.
Control interfaces
av_mm_control_agent_address In 8 94 Avalon memory-mapped agent address
av_mm_control_agent_write In 1 Avalon memory-mapped agent write.
av_mm_control_agent_writedata In 32 Avalon memory-mapped agent write data.
av_mm_control_agent_byteenable In 4 Avalon memory-mapped agent byte enable.
av_mm_control_agent_read In 1 Avalon memory-mapped agent read.
av_mm_control_agent_readdata Out 32 Avalon memory-mapped agent read data.
av_mm_control_agent_readdatavalid Out 1 Avalon memory-mapped agent read.
av_mm_control_agent_waitrequest Out 1 Avalon memory-mapped agent wait request.
fsync_in_read In 1 Conduit.
frame_reader_int_irq Out 1 Conduit.
Intel FPGA streaming video interface
axi4s_vid_out_tdata Out 95 AXI4-S data out.
axi4s_vid_out_tvalid Out 1 AXI4-S data valid.
axi4s_vid_out_tuser[0] Out 1 AXI4-S start of video frame.
axi4s_vid_out_tuser[1] Out 1 AXI4-S control or data packet.
axi4s_vid_out_tuser[N-1:2] Out 96 Unused.
axi4s_vid_out_tlast Out 1 AXI4-S end of packet.
axi4s_vid_out_tready In 1 AXI4-S data ready.

Avalon memory-mapped host interfaces

Widths for address, data, and burst count buses are as you specify in the GUI. The table shows example widths.

mem_clock_clk In 1 Optional host interface clock.
mem_reset_reset In 1 Optional host interface reset.
av_mm_mem_read_host_address Out 32 Avalon memory-mapped host address.
av_mm_mem_read_host_read Out 1 Avalon memory-mapped host read.
av_mm_mem_read_host_burstcount Out 5 Avalon memory-mapped host read burst count.
av_mm_mem_read_host_readdata In 64 Avalon memory-mapped host read data.
av_mm_mem_read_host_readdatavalid In 1 Avalon memory-mapped host read data valid.
av_mm_mem_read_host_waitrequest In 1 Avalon memory-mapped host wait request.
94 Address width depends on the setting of Maximum number of buffer sets compile-time parameter.
95

The equation gives all axi4s_vid_out_tdata widths in these interfaces:

max (floor(((bits per color sample x number of color planes x pixels in parallel) + 7) / 8) x 8, 16)

96

This equation gives all axi4s_vid_out_tuser widths in these interfaces N = ceil (tdata width / 8)