Visible to Intel only — GUID: nyg1637769028434
Ixiasoft
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Bits per Color Sample Adapter Intel FPGA IP
11. Chroma Key Intel® FPGA IP
12. Chroma Resampler Intel® FPGA IP
13. Clipper Intel® FPGA IP
14. Clocked Video Input Intel® FPGA IP
15. Clocked Video to Full-Raster Converter Intel® FPGA IP
16. Clocked Video Output Intel® FPGA IP
17. Color Space Converter Intel® FPGA IP
18. Deinterlacer Intel® FPGA IP
19. FIR Filter Intel® FPGA IP
20. Frame Cleaner Intel® FPGA IP
21. Full-Raster to Clocked Video Converter Intel® FPGA IP
22. Full-Raster to Streaming Converter Intel® FPGA IP
23. Genlock Controller Intel® FPGA IP
24. Generic Crosspoint Intel® FPGA IP
25. Genlock Signal Router Intel® FPGA IP
26. Guard Bands Intel® FPGA IP
27. Interlacer Intel® FPGA IP
28. Mixer Intel® FPGA IP
29. Pixels in Parallel Converter Intel® FPGA IP
30. Scaler Intel® FPGA IP
31. Stream Cleaner Intel® FPGA IP
32. Switch Intel® FPGA IP
33. Tone Mapping Operator Intel® FPGA IP
34. Test Pattern Generator Intel® FPGA IP
35. Video and Vision Monitor Intel FPGA IP
36. Video Frame Buffer Intel® FPGA IP
37. Video Frame Reader Intel FPGA IP
38. Video Frame Writer Intel FPGA IP
39. Video Streaming FIFO Intel® FPGA IP
40. Video Timing Generator Intel® FPGA IP
41. Warp Intel® FPGA IP
42. Design Security
43. Document Revision History for Video and Vision Processing Suite User Guide
23.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
23.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
23.4.3. Setting the VCXO hold over
23.4.4. Restarting the Genlock Controller IP
23.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
23.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
23.4.7. Disturbing a Reference Clock (a cable pull)
Visible to Intel only — GUID: nyg1637769028434
Ixiasoft
21.4. Full-Raster to Clocked Video Converter Registers
The IP allows runtime configuration of parameters using the Avalon memory-mapped CPU register interface. Unless stated, all registers are 32-bit wide.
Register | Offset | Access | Description |
---|---|---|---|
CVI specific registers | |||
Reg_CVI_Legacy_0 | 0x140 | RW | Drives legacy CVI conduit output signals and returns the current values. |
Reg_CVI_Legacy_1 | 0x144 | RW | Drives legacy CVI conduit output signals and returns the current values. |
Reg_CVI_Legacy_2 | 0x148 | RW | Drives legacy CVI conduit output signals and returns the current values. |
CVO specific registers | |||
Reg_CVO_Legacy_0 | 0x14C | RW | The current value of the CVO conduit side-band signals vid_sof. |
Name | Bits | Attribute | Description |
---|---|---|---|
CVI SOF | 0 | RO | The current value of the CVI legacy signal sof. |
CVI SOF Locked | 1 | RO | The current value of the CVI legacy signal sof_locked. |
CVI Overflow | 2 | RO | The current value of the CVI legacy signal overflow. |
CVI Clipping | 3 | RO | The current value of the CVI legacy signal clipping. |
CVI Padding | 4 | RO | The current value of the CVI legacy signal padding. |
CVI refclk_div | 5 | RO | The current value of the CVI legacy signal refclk_div. |
Reserved | 7:6 | - | Reserved. |
CVI video locked | 8 | RW | Drives legacy CVI conduit signal vid_locked. |
Reserved | 15:9 | - | Reserved. |
CVI color encoding | 23:16 | RW | Drives legacy CVI conduit signal vid_color_encoding. |
CVI bit width | 31:24 | RW | Drives legacy CVI conduit signal vid_bit_width. |
Name | Bits | Attribute | Description |
---|---|---|---|
CVI vid std | Width of vid_std -1:0 | RW | Drives legacy CVI conduit signal vid_std. |
CVI HDMI duplication | 19:16 | RW | Drives legacy CVI conduit signal vid_hdmi_duplication. |
Reserved | 23:20 | - | Reserved. |
CVI HD not SD | 24 | RW | Drives legacy CVI conduit signal vid_hd_sdn. |
Reserved | 31:25 | - | Reserved. |
Name | Bits | Attribute | Description |
---|---|---|---|
Total Pixels | 15:0 | RW | Drives legacy CVI conduit signal total_sample_count. |
Total Lines | 31:16 | RW | Drives legacy CVI conduit signal total_line_count. |
Name | Bits | Attribute | Description |
---|---|---|---|
CVO SOF | 0 | RW | Drives legacy clocked video output conduit signal vid_sof. |
CVO SOF Locked | 1 | RW | Drives legacy clocked video output conduit signal vid_sof_locked. |
CVO Underflow | 2 | RW | Drives legacy clocked video output conduit signal underflow. |
CVO vco clock divide | 3 | RW | Drives legacy clocked video output conduit signal vid_vcoclk_div. |
CVO mode change | 4 | RW | Drives legacy clocked video output conduit signal vid_mode_change. |
Reserved | 15:5 | - | Reserved. |
CVO video standard | Width of vid_std+15:16 | RW | Drives legacy clocked video output conduit signal vid_std. |