Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide

16.1. About the Clocked Video Output IP

The Clocked Video Output Intel FPGA IP merges the pixel data from an a lite or full variant of the Intel FPGA streaming video protocol with the real-time video signals from a reference full-raster stream. The output is a full-raster bus that you can connect directly to an Intel Protocol IP.

Another IP can provide the reference full-raster stream or an optional internal Video Timing Generator Intel FPGA IP can generate the reference stream.

You can select the optional internal video timing generator from the IP GUI. It is a version of the video timing generator IP that provides the same features and functionalities (refer to Video Timing Generator Intel FPGA IP).

Second Input Fall Back

The IP provides an optional second video streaming input. If the primary input stream fails, the IP automatically changes to use the second input. If the second input also fails, or is not used, the IP produces black. You can configure the exact pixel value for black at build time and via the processor interface at runtime.

By default, when the primary video input relocks to the timing reference the IP automatically changes back to the primary video input at the start of the next frame. However, you can change the default behavior via the processor interface. Using the processor interface, you can manually control when the IP changes from the test pattern input back to the video input. You can force the IP to select either the main video input, the test pattern input, or black.

Pixels in Parallel Support

The IP supports any number of pixels in parallel from 1 to 8. The raster dimensions have no restrictions on the number of pixels in parallel. The raster width does not have to be an integer multiple of pixels in parallel.

The pixel input stage contains a barrel shift to align the lite or full streams with the full-raster stream.