Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide

38.1. About the Video Buffer Writer IP

The IP receives frames or fields from an Intel FPGA streaming video input and stores them in external memory. The frame writer has a host Avalon memory-mapped interface to allow connection to an external memory interface and an agent Avalon memory-mapped interface to allow run-time control.

The frame writer supports:

  • Maximum frame resolutions of 16,384 by 16,384 pixels with 1 to 8 pixels in parallel and any color space
  • Writing of progressive frames or interlaced fields
  • Configurable memory packing scheme
  • Runtime location of frame or field anywhere in memory
  • Configurable interrupt on completion of frame, field, or line writes
  • Free running or single-shot mode for event capture
  • Configurable discarding of broken fields or frames
  • Automatic receiving and storing of up to 16,777,215 fields or frames contiguously in memory with no host control

The IP is available as full or lite variants. For more information on full and lite, refer to the Intel FPGA Streaming Video Protocol Specification. The Video Frame Writer IP takes resolution information from the configurable buffer set registers.

An Avalon memory-mapped interface allows you to configure buffer sets and change the operating mode at run time. You must have this interface for both full and lite variants.

For details about latency and reset behavior for the Video Frame Writer, refer to Video and Vision IPs Functional Description.