Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
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21.3.1. Full Raster to Clocked Video Converter Interfaces

The IP has three functional interfaces:
  • Full raster data input interface for video IOs
  • Intel clocked video data output interface for video IOs
  • Avalon memory-mapped CPU interface
Table 368.   Clocks and Resets
Name Direction Width Description
vid_clock Input 1

When you select Lite and CVI, this is the video clock for the lite and clocked video outputs, and the streaming full raster input.

When you select CVO, the clocked video outputs bus can contain an optional input clock. If you turn on the clocked video output input clock, this signal is a dummy signal retained for Platform Designer connectivity. The IP uses the video clock included in the cv_vid_out conduit.

vid_reset Input 1 Reset for vid_clock domain.
cpu_clock Input 1 Optional control interface clock.
cpu_reset Input 1 Optional control interface reset.
cv_clk_out Output 1 A copy of the video clock that the IP uses.
Table 369.  Control InterfaceThis interface is only available if you select True for Memory-mapped control interface.
Name Direction Width Description
av_mm_cpu_agent_address Input 7 Control agent port Avalon memory-mapped address bus. Specifies a word offset into the slave address space.
av_mm_cpu_agent_read Input 1 Control agent port Avalon memory-mapped read signal. When you assert this signal, the control port drives new data onto the read data bus.
av_mm_cpu_agent_readdata Output 32 Control agent port Avalon memory-mapped read data bus. These output lines are used for read transfers.
av_mm_cpu_agent_waitrequest Output 1 Control agent port Avalon memory-mapped wait request bus. This signal indicates that the slave is stalling the host transaction.
av_mm_cpu_agent_write Input 1 Control agent port Avalon memory-mapped write signal. When you assert this signal, the control port accepts new data from the write data bus.
av_mm_cpu_agent_writedata Input 32 Control agent port Avalon memory-mapped write data bus. These input lines are used for writing transfers.
av_mm_cpu_agent_byteenable Input 4 Control agent port Avalon memory-mapped byte enable bus. These lines indicate which bytes are selected for write and read transactions.
Table 370.  Intel FPGA streaming full raster video interface
Name Direction Width Description
axi4s_fr_vid_in_tvalid Input 1 AXI4-S full raster data valid.
axi4s_fr_vid_in_tready Output 1 Optional AXI4-S full raster data ready.
axi4s_fr_vid_in_tdata Input 55 AXI4-S full raster data in.
axi4s_fr_vid_in_tlast Input 1 AXI4-S end of full raster packet.
axi4s_fr_vid_in_tuser[0] Input 56 AXI4-S start of full raster video frame.
Table 371.   CV Lite Streaming Video Interface This interface is only available if you select Lite for CV Bus Style.
Name Direction Width Description
cv_vid_out_h Output Pixels in parallel When asserted, the video is in a horizontal blanking.
cv_vid_out_v Output Pixels in parallel When asserted, the video is in a vertical blanking.
cv_vid_out_h_sync Output Pixels in parallel When asserted, the video is in a horizontal synchronization period.
cv_vid_out_v_sync Output Pixels in parallel When asserted, the video is in a vertical synchronization period.
cv_vid_out_f Output Pixels in parallel When asserted, the video is interlaced and in field 1. When deasserted, the video is either progressive or interlaced and in field 0.
cv_vid_out_active Output Pixels in parallel When asserted, the video is in an active picture period (not horizontal or vertical blanking). You must drive this signal for correct operation of the IPs.
cv_vid_out_data Output 57 Pixel data.
cv_vid_out_valid Output 1 When asserted, the output is valid.
cv_vid_out_ready Input 1 When asserted, the IP can drive new data. When deasserted, the IP can drive no new data.
Table 372.   Clocked Video Input Streaming Video Interface This interface is only available if you select CVI for CV Bus Style.
Name Direction Width Description
cv_vid_out_vid_clk Input 1 The pixel synchronous clock.
cv_vid_out_vid_h_sync Output Pixels in parallel When asserted, the video is in a horizontal blanking or synchronization period.
cv_vid_out_vid_v_sync Output Pixels in parallel When asserted, the video is in a vertical blanking or synchronization period.
cv_vid_out_vid_f Output Pixels in parallel When asserted, the video is interlaced and in field 1. When deasserted, the video is either progressive or interlaced and in field 0.
cv_vid_out_vid_data Output 58 Pixel data.
cv_vid_out_vid_de Output Pixels in parallel When asserted, the video is in an active picture period (not horizontal or vertical blanking).
cv_vid_out_vid_datavalid Output 1 When asserted, the output is valid.
cv_vid_out_vid_locked Output 1 Unused legacy signal.
cv_vid_out_vid_hd_sdn Output 1 Unused legacy signal.
cv_vid_out_vid_std Output User Specified Unused legacy signal.
cv_vid_out_vid_color_encoding Output 8 Unused legacy signal.
cv_vid_out_vid_bit_width Output 8 Unused legacy signal.
cv_vid_out_vid_total_sample_width Output 16 Indicates the total (active + blanking) width of the raster.
cv_vid_out_vid_total_line_count Output 16 Indicates the total (active + blanking) height of the raster.
cv_vid_out_vid_hdmi_duplication Output 4 Unused legacy signal.
cv_vid_out_sof Input 1 Unused legacy signal.
cv_vid_out_sof_locked Input 1 Unused legacy signal.
cv_vid_out_refclk_div Input 1 Unused legacy signal.
cv_vid_out_clipping Input 1 Unused legacy signal.
cv_vid_out_padding Input 1 Unused legacy signal.
cv_vid_out_overflow Input 1 Unused legacy signal.
Table 373.  Clocked Video Output Streaming Video InterfaceThis interface is only available if you select CVO for CV Bus Style.
Name Direction Width Description
cv_vid_out_vid_clk Input 1 Pixel synchronous clock.
cv_vid_out_vid_h Output Pixels in parallel When asserted, the video is in a horizontal blanking.
cv_vid_out_vid_v Output Pixels in parallel When asserted, the video is in a vertical blanking.
cv_vid_out_vid_h_sync Output Pixels in parallel When asserted, the video is in a horizontal synchronization period.
cv_vid_out_vid_v_sync Output Pixels in parallel When asserted, the video is in a vertical synchronization period.
cv_vid_out_vid_f Output Pixels in parallel When asserted, the video is interlaced and in field 1. When deasserted, the video is either progressive or interlaced and in field 0.
cv_vid_out_vid_data Output 59 Pixel data.
cv_vid_out_vid_datavalid Output Pixels in parallel When asserted, the output is valid.
cv_vid_out_underflow Output 1 Unused legacy signal.
cv_vid_out_vid_mode_change Output 1 Unused legacy signal.
cv_vid_out_vid_vcoclk_div Output 1 Unused legacy signal.
cv_vid_out_vid_sof_locked Output 1 Unused legacy signal.
cv_vid_out_vid_sof Output 1 Unused legacy signal.
cv_vid_out_vid_std Output 6 Unused legacy signal.
55

The equation gives the sizes of all tdata widths in these interfaces;

max (floor(((bits per color sample x (number of color planes+1) x pixels in parallel) + 7) / 8) x 8, 16)

56

The equation gives the sizes of all tuser widths in these interfaces

N = ceil (tdata width / 8)

57

The equation gives the data width size:

width = (bits per color sample X number of color planes X pixels in parallel)

58

The equation gives the data width size:

width = (bits per color sample X number of color planes X pixels in parallel)

59

The equation gives the data width sizes:

width = (bits per color sample X number of color planes X pixels in parallel)