Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
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19.3.3. FIR Coefficient Specification

You can specify the FIR filter IP filtering operation coefficients as fixed values that the IP applies on reset if Use memory initialization coefficients file is on. Also, you can specify them at run time when you turn on Memory-mapped control interface and Update coefficients at run time.

The IP requires you to define a fixed-point type for the coefficients. The user-entered coefficients (shown as white boxes in the parameter editor) are rounded to fit in the chosen coefficient fixed-point type (shown as purple boxes in the parameter editor).

  • For run-time editable coefficients, you must enter the desired coefficient values through an Avalon memory-mapped agent control interface at run time, and you can update the coefficient values as often as once per frame.
    Note: Without enabling the coefficient initialization file, the coefficient values all revert to undefined after every reset, so you must initialize coefficients at least once on start-up.
  • To keep the register map as small as possible and to reduce complexity in the hardware, the IP reduces the number of coefficients that it edits at run time when you turn on any of the symmetric modes.
  • For T unique coefficient values after symmetry, the register map contains T addresses into which you should write coefficients, starting at address 7 and finishing at T+ 6.

Fixed Coefficient

For fixed coefficients, you specify the values for the coefficients with a comma-separated .csv text file. The selected coefficient values take effect immediate effect at reset.

Regardless of the symmetry mode, the text file must contain a full listing of all the coefficients in the N×M array i.e. the file must always contain N×M comma-separated values. When the .csv file is parsed in Platform Designer to create the list of compile time coefficients, the IP checks the values entered against the selected symmetry mode and provides warnings if the coefficients are not symmetric across the selected axes. The values specified in the .csv file must be in their unquantized format. For example, if you want a value of 1.7 for a given coefficient, the value in the file should be 1.75. When the file is parsed in Platform Designer, the coefficients automatically quantize according to the precision you specify.

Note: The quantization process selects the closest value available in the given precision format. If you select the coefficients arbitrarily without reference to the available precision, the quantized value may differ from the desired value.

Run-time Editable Coefficients

To keep the register map as small as possible and to reduce complexity in the hardware, the number of coefficients that are edited at run time is reduced when you turn on any of the symmetric modes.

If the IP has T unique coefficient values after symmetry, the register map contains T addresses into which you should write coefficients, starting at address 0x200 and finishing at 0x200 + (4*(T-1)).

Write coefficient index 0 (as described in the symmetry section) to address 0x200. Then write each successively indexed coefficient at each following address. The updated coefficient set takes effect immediately. To avoid the IP updating coefficients in the middle of a frame, Intel recommends reading bit 3 of the status register to check that the algorithmic core is idle before writing new coefficients.

Note: The coefficient values you write to the register map must be in prequantized format as the hardware cost to implement quantization on floating point values is prohibitive.