Visible to Intel only — GUID: czq1683034880228
Ixiasoft
Visible to Intel only — GUID: czq1683034880228
Ixiasoft
10.3. Bits per Color Sample Adapter IP Interfaces
Signal name | Direction | Width | Description |
---|---|---|---|
Clocks and resets | |||
main_clock_clk | In | 1 | AXI4-S processing clock. |
main_reset_rst | In | 1 | AXI4-S processing reset. |
Control interfaces | |||
av_mm_control_agent_address | In | 7 | Avalon memory-mapped agent address. |
av_mm_control_agent_write | In | 1 | Avalon memory-mapped agent write. |
av_mm_control_agent_writedata | In | 32 | Avalon memory-mapped agent write data. |
av_mm_control_agent_byteenable | In | 4 | Avalon memory-mapped agent byte enable. |
av_mm_control_agent_read | In | 1 | Avalon memory-mapped agent read. |
av_mm_control_agent_readdata | Out | 32 | Avalon memory-mapped agent read data. |
av_mm_control_agent_readdatavalid | Out | 1 | Avalon memory-mapped agent read data valid |
av_mm_control_agent_waitrequest | Out | 1 | Avalon memory-mapped agent wait request. |
Intel FPGA streaming video interfaces |
|||
axi4s_vid_in_tdata | In | 8 | AXI4-S data in |
axi4s_vid_in_tvalid | In | 1 | AXI4-S data valid |
axi4s_vid_in_tuser | In | 9 | AXI4-S tuser tuser[0] indicates start of video frame when asserted tuser[1] indicates the start of a nonvideo packet when asserted |
axi4s_vid_in_tlast | In | 1 | AXI4-S end of packet |
axi4s_vid_in_tready | Out | 1 | AXI4-S data ready |
axi4s_vid_out_tdata | Out | 0 | AXI4-S data in |
axi4s_vid_out_tvalid | Out | 1 | AXI4-S data valid |
axi4s_vid_out_tuser | Out | 9 | AXI4-S tuser tuser[0] indicates start of video frame when asserted tuser[1] indicates the start of a non-video packet when asserted |
axi4s_vid_out_tlast | Out | 1 | AXI4-S end of packet |
axi4s_vid_out_tready | In | 1 | AXI4-S data ready |
The equation gives all tdata widths in these interfaces:
max (ceil((bits per color sample x number of color planes) / 8) x pixels in parallel x 8, 16)