Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide

14.5. Clocked Video Input IP Registers

The IP allows runtime configuration of parameters via Avalon memory-mapped processor register interface.
Table 164.  Clocked Video Input IP Registers
Offset Register Access Description
Parameterization registers
0x000 VID_PID RO Read this register to retrieve clocked video input product ID. This register always returns 0x6FA7_0170.
0x004 VERSION_NUMBER RO

Read this register to retrieve the version information for this IP.

0x008-

0x014

RESERVED RO
0x018 NUMBER OF PIXELS IN PARALLEL RO Read this register to determine the number of pixels processed per clock cycle.
0x01C NUMBER OF COLOR PLANES RO Read this register to determine the number of color planes.
0x020 NUMBER OF BITS PER COLOR SAMPLE RO Read this register to determine the number of bits per color sample
0x024 AXI4-S FR INTERFACE TREADY RO Read this register to determine if the full-raster interface includes the TREADY conduit
0x028 OUTPUT VIDEO LINE BUFFER DEPTH RO Read this register to determine the depth of the output line buffer
0x02C VIDEO TELEMETRICS INFORMATION RO Read this register to determine if the optional logic to retrieve video timing information was included for this IP
0x030 OUTPUT CLOCK FREQUENCY RO Read this register to determine the output clock frequency
Core Specific Registers
0x148 Control RW Sets the IP control mode of operation
0x14C Status RW Returns the status of the IP
0x150 Interrupt_Alarm RW Interrupt status and clear bits
0x154 Horizontal_sample_count RO Returns the detected width count per line of the video streams.
0x158 Active_line_count RO Returns the detected height count per frame of the video streams excluding blanking.
0x15C Total_line_count RO Returns the detected height count per frame of the video streams including blanking.
0x160 Ref_lock_cfg1 RW The IP reference width and height values to assert the video locked signal
0x164 Ref_lock_cfg2 RW The IP reference number of frames and lines values to assert the video locked signal
0x168 Clk_in_freq_count RO Returns the detected frequency value of the input clock
0x16C Tpg_cfg1 RW Configure the value of the color plane 4 and color plane 3
0x170 Tpg_cfg2 RW Configure the value of the color plane 2 and color plane 1
0x174-0x184 Reserved -
0x188 Total_fr_pixel_count RO Returns the detected total number of pixels on the input full-raster frame including blanking
0x18C Total_active_pixel_count RO Return the detected total number of pixels on the input full-raster frame excluding blanking
0x190 Fr_pixel_line_count RO Returns the detected total number of pixels per line including and excluding blanking.
0x194 Hpulse_count RO Returns the Hsync width value if the video format uses Sync timing mode, otherwise it returns the total horizontal blanking period.
0x198 Hbp_hfp_count RO Returns the horizontal back porch width value if the video format uses Sync timing mode, otherwise it returns 0.
0x19C f0f1_vfp_count RO Returns the vertical front porch value for field 0 and field 1.
0x1A0 f0f1_vpulse_count_reg RO Returns the Vsync value for field 0 and field 1.
0x1A4 f0f1_vbp_count_reg RO Returns the vertical back porch value for field 0 and field 1.
0x1A8 Hpulse_ref RW Reference value for the expected Hsync parameter. 24
0x1AC Hbp_hfp_ref RW Reference value for the expected horizontal front and back porch parameters.24
0x1B0 f0f1_vfp_ref RW Reference value for the expected vertical front porch parameter. 24
0x1B4 f0f1_vpulse_ref RW Reference value for the expected Vsync parameter. 24
0x1B8 f0f1_vbp_ref RW Reference value for the expected vertical back porch parameter. 24
0x1BC f0f1_fps_cnt RO Returns the number of frames per second value for field 0 and field 1.

Register Bit Descriptions

Table 165.  Vid_pid
Bits Description
31:0 Product Identification Number

Table 166.  Version_number_pid
Bits Description
31:0 IP Version Number
Table 167.  NUMBER OF PIXELS IN PARALLEL
Bits Description
31:0 The number of pixels transmitted every clock cycle.
Table 168.  NUMBER OF COLOR PLANES
Bits Description
31:0 The number of color planes per sample at the input
Table 169.  NUMBER OF BITS PER COLOR SAMPLE
Bits Description
31:0 The number of bits per color sample
Table 170.  AXI4-S FR INTERFACE TREADY
Bits Description
31:0 Enable the TREADY signal as part of the full-raster interface
Table 171.  OUTPUT VIDEO LINE BUFFER DEPTH
Bits Description
31:0 The maximum depth of the output video line buffer
Table 172.  VIDEO TELEMETRICS INFORMATION
Bits Description
31:0 Enable the video telemetrics information logic
Table 173.  OUTPUT CLOCK FREQUENCY
Bits Description
31:0 The output clock frequency in Hz
Table 174.  Control
Bits Name Description
23:16 f0f1_fps_ref_cnt

Setting these bits with the minimum expected number of frames per second values for F0 and F1 enables the automatic detection of interlaced video formats

7 ext_locked_ena Setting this bit enables an external video locked signal to indicate when a stable video stream is present on the input.
6 hsync_pol If auto polarity detection is off, set this bit to override the polarity for the hsync/hpulse signal
5 vsync_pol If auto polarity detection is off, set this bit to override the polarity for the vsync/vpulse signal
4 auto_pol_dect Set this bit to turn on the video sync autopolarity detection.
3 mux_out_sel Set this bit to turn on the output frame cleaner.
2 irq2_ena Set this bit to turn on the end of frame video interrupt.
1 irq1_ena Set this bit to turn on the status update interrupt
0 Go bit Set this bit to 1 to start IP data output on the next video frame boundary.
Table 175.  Status
Bits Name Description
11 vid_in_clk_stopped

This bit indicates if the input video clock has stopped working

10 fr_interlaced_detected This bit indicates if the input video format has been autodetected as interlaced video format
9 hsync_pol_detc This bit indicates the detected polarity for the horizontal signal
8 vsync_pol_detc This bit indicates the detected polarity for the vertical signal
7 drop_vid This bit indicates that a frame was not completed
6 - Reserved
5 external_vid_locked This bit indicates if the external video locked has been asserted
4 internal_vid_locked This bit indicates if the external video locked has been asserted
3 overflow_sticky This bit indicates if a FIFO overflow occurs. Writing 1 to this bit clears it
2 vid_sync_mode This bit indicates if the input video frame is using Blank timing or Sync timing
1 interlaced_detected This bit indicates if an interlaced format has been detected
0 Status This bit indicates if the input resolution has changed.
Table 176.  Interrupt_Alarms
Bits Name Description
14 hfp_alarm_sticky This bit indicates that the reference hfp counter is not matching the actual hfp counter. Set this bit to 1 to clear it.
13 hpulse_alarm_sticky This bit indicates that the reference hpulse counter is not matching the actual hpulse counter. Set this bit to 1 to clear it.
12 hbp_alarm_sticky . This bit indicates that the reference hbp counter is not matching the actual hbp counter. Set this bit to 1 to clear it.
11 f0_vfp_alarm_sticky This bit indicates that the reference vfp counter is not matching the actual vfp counter. Set this bit to 1 to clear it.
10 f0_vpulse_alarm_sticky This bit indicates that the reference vpulse counter is not matching the actual vpulse counter. Set this bit to 1 to clear it.
9 f0_vbp_alarm_sticky . This bit indicates that the reference vbp counter is not matching the actual vbp counter. Set this bit to 1 to clear it.
8 f1_vfp_alarm_sticky This bit indicates that the reference vfp counter is not matching the actual vfp counter. Setting this bit to 1 to clear it.
7 f1_vpulse_alarm_sticky This bit indicates that the reference vpulse counter is not matching the actual vpulse counter. Set this bit to 1 to clear it.
6 f1_vbp_alarm_sticky . This bit indicates that the reference vbp counter is not matching the actual vbp counter. Set this bit to 1 to clear it.
5 video_width_alarm_sticky This bit indicates that the reference width counter is not matching the actual width counter. Set this bit to 1 to clear it.
4 video_height_alarm_sticky This bit indicates that the reference height counter is not matching the actual height counter. Set this bit to 1 to clear it.
3 video_frames_alarm_sticky This bit indicates that the reference frame counter is not matching the actual frame counter. Set this bit to 1 to clear it.
2 video_lines_alarm_sticky This bit indicates that the reference line counter is not matching the actual line counter. Set this bit to 1 to clear it.
1 eof_sticky This bit indicates the end of frame. Set this bit to 1 to clear it.
0 irq_status_sticky This bit indicates a change of input video resolution. Set this bit to 1 to clear it.
Table 177.  Horizontal_sample_count
Bits Description
31:16 The total number of pixels per line
15:0 The active number of pixels per line
Table 178.  Active_line_count
Bits Description
31:16 The active number of lines for field 0
15:0 The active number of lines for field 1
Table 179.  Total_line_count
Bits Description
31:16 The total (blanking + active) number of lines for field 0
15:0 The total (blanking + active) number of lines for field 1
Table 180.  Ref_lock_cfg1
Bits Description
31:16 The expected output video height to assert video locked signal
15:0 The expected output video width to assert video locked signal
Table 181.  Ref_lock_cfg2
Bits Description
31:16 The number of consecutive valid frames before asserting video locked signal
15:0 The number of consecutive valid lines before asserting video locked signal
Table 182.  Clk_in_freq_count
Bits Description
31:0 The value of input clock frequency in Hz
Table 183.  Tpg_cfg1_reg
Bits Description
31:16 Pixel value for the color plane # 4
15:0 Pixel value for the color plane # 3
Table 184.  Tpg_cfg2
Bits Description
31:16 Pixel value for the color plane # 2
15:0 Pixel value for the color plane # 1
Table 185.  Total_fr_pixel_count
Bits Description
31:0 Total number of full-raster pixels per frame
Table 186.  Total_active_pixel_count
Bits Description
31:0 Total number of actives pixels per frame
Table 187.  Fr_pixel_line_count
Bits Description
31:16 Full-raster blanking pixels per line
15:0 Full-raster blanking lines per frame
Table 188.  Hpulse_count
Bits Description
31:16

Total number of active lines per frame

15:0 Horizontal (H) counter
Table 189.  Hbp_hfp_count
Bits Description
31:16 Horizontal front porch counter
15:0 Horizontal back porch counter
Table 190.  F0f1_vfp_count
Bits Description
31:16 Vertical front porch counter for field 0
15:0 Vertical front porch counter for field 1
Table 191.  F0f1_vpulse_count
Bits Description
31:16 Vertical reference for field 0
15:0 Vertical counter for field 1
Table 192.  F0f1_vbp_count
Bits Description
31:16 Vertical back porch counter for field 0
15:0 Vertical back porch counter for field 1
Table 193.  Hpulse_ref
Bits Description
15:0 Horizontal (H) reference counter
Table 194.  Hbp_hfp_ref
Bits Description
31:16 Horizontal front porch reference counter
15:0 Horizontal back porch reference counter
Table 195.  F0f1_vfp_ref
Bits Description
31:16 Vertical front porch reference counter for field 0
15:0 Vertical front porch reference counter for field 1
Table 196.  F0f1_vpulse_ref
Bits Description
31:16 Vertical (V) reference counter for field 0
15:0 Vertical (V) reference counter for field 1
Table 197.  F0f1_vbp_ref
Bits Description
31:16 Vertical back porch reference counter for field 0
15:0 Vertical back porch reference counter for field 1
Table 198.  f0f1_fps_cnt
Bits Description
31:16

Number of frames per second detected for field 0

15:0

Number of frames per second detected for field 1

24 If the corresponding alarm is on, and the detected value do not match this register, the IP asserts a sticky bit to indicate a mismatch.