Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
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3.1. Auxiliary Control Packets

Full variant video and vision processing IPs may transmit other types of auxiliary control packets, such as timestamp packets to synchronize with audio or other types of auxiliary control packets. You can define auxiliary control packets, which contain information such as active format description (AFD) or closed captioning.

IPs propagate auxiliary control packets with the video data packets. IPs such as the video frame buffer observe rules that determine how to handle auxiliary control packets.

Figure 6. Auxiliary control packet positions.The figure shows an example where two auxiliary control packets precede an image information packet and a third precedes an end of frame packet.

Auxiliary control packets in between image information packets and video packets, or in between adjacent data packets contravene the Intel FPGA streaming video protocol. IPs presented with metapackets in these locations exhibit undefined behavior and the system may break.

In the figure, the video field described by the image information packets, video and end of field packets has three auxiliary control packets. If the frame buffer receives these packets, the IP processes them in the same way as the video field. The IP potentially drops or repeats them.

Auxiliary control packets only occupy the low 16 bits of the TDATA bus.

For TDATA widths greater than 16 bits, to adapt to a different interface, do not use standard AXI4-Stream converters. Use the protocol converter IPs.