Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
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26.1. About the Guard Bands IP

The IP compares each color plane in the input video to upper and lower guard band values. If the value in any color plane exceeds the upper guard band, the IP replaces the value with the upper guard band. Similarly, if the value in any color plane falls below the lower guard band, the IP replaces the value with the lower guard band.

You can specify different guard band values for each color plane. You can alter these values at run-time through the Avalon memory-mapped interface. Otherwise, the guard band values are fixed at compile-time.

The input can be unsigned data or signed 2’s complement data for which the IP converts the data to an unsigned format (by adding half the maximum range) before applying guard bands. The guard bands are specified as unsigned values.

The IP can drive the output data as signed data but, as with signed input data, the IP applies guard bands on the unsigned data before it converts it to signed output. The IP converts the output data to a signed format by subtracting half the maximum range after applying guard bands.

You cannot select both signed input and signed output data. The IP prepares data for other video and vision processing IPs, which primarily operate on unsigned data. You can place this IP before and after another video and vision IP, configuring the first for signed input and the second to use signed output data.