Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
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32.1. About the Switch IP

The Switch Intel FPGA IP allows connections between video inputs and outputs to provide cross-point switching, multipoint switching, and video broadcast functions.

The switch supports:

  • Up to 8 independent video outputs.
  • Up to 8 independent video inputs, configurable to block, consume or drive any number of the 1-8 video outputs.
  • Clean or crash switching of video outputs.
  • Lite, full, or full raster variants.
  • Optional tready signals for full raster variants.
  • Clean switching on field boundaries.
  • Configurable line switching for lite or full raster variants.
  • Propagation of auxiliary control packets with their associated field, for full variants.
  • 1 to 8 pixels in parallel and any color space.
  • Autoconsume inputs for full variants with clean switching

For more information on lite, full, and full raster variants refer to the Intel FPGA Streaming Video Protocol Specification. The switch IP takes input resolution information from image information packets or from the register interface for lite and full raster variants.

An Avalon memory-mapped interface allows the run-time configuration of the switch.

For information about the reset behavior for the switch, refer to Reset Behavior in Video and Vision IPs Functional Description.