Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
Give Feedback

9.2. AXI-Stream Broadcaster IP Parameters

The IP offers compile-time parameters.
Table 55.  AXI-Stream Broadcaster IP Parameters
Parameter Values Description
Video Data Format
Bits per color sample 8 to 16 Select the number of pixels in parallel.
Number of color planes 1 to 4 Select the number of color planes per pixel.
Number of pixels in parallel 1 to 8 Select the number of bits per color sample.
Settings (Global)
Number of outputs 1 to 32 The number of broadcaster outputs
VVP interface type Full, Lite or Full Raster (FR) The interface type of the AXI4-S input and outputs
Input TREADY On or off The input has TREADY
Global stall On or off If at least one output's TREADY signal is low, deassert the input TREADY and stall all output FIFO buffers.
Settings (Per Output Interface)
Output TREADY On or off The output has TREADY
Output FIFO On or off Add a FIFO buffer on the output interface to handle TREADY backpressure
Output FIFO depth

16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768

The maximum depth of the output FIFO buffer for handling TREADY backpressure
Figure 17. AXI-Stream Broadcaster IP Parameter GUI