Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
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27.4. Interlacer IP Registers

Each register is either read-only (RO) or read-write (RW).

In the software API these register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE, or INTEL_VVP_INTERLACER as appropriate and with an optional REG suffix

Address Register Access Description
Lite Full
Parameterization registers
0x0000 PROD_ID RO

Read this register to retrieve the interlacer product ID.

This register always returns 0x6AF7_0232.

0x0004 VER RO

Read this register to retrieve the version information for the interlacer.

0x0008 LITE_MODE RO Read this register to determine if lite mode is on. This register returns 0 when you turn off lite mode and 1 when you turn on lite mode.
0x000C DEBUG_ENABLED RO

Read this register to determine if debug features are on.

This register returns 1 if Debug features are on and 0 otherwise

0x0010 to 0x011F unused

Control and debug registers

For more details of these registers, refer to Image information control packets in the Intel FPGA Streaming Video Protocol Specification You must turn on Debug features to read the values in these registers. If Debug features are off, reads to these registers return undefined data. The only exception is the STATUS register, whose value you can always read.

0x0120 IMG_INFO_WIDTH RW RO

When you turn on lite mode , use this register to set the expected width of incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the width that the interlacer derives from information in the image information control packet.

0x0124 IMG_INFO_HEIGHT RW RO

When you turn on lite mode , use this register to set the expected height of incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the height that the interlacer derives from information in the image information control packet.

0x0128 IMG_INFO_INTERLACE RW RO

When you turn on lite mode , use this register to set the expected interlace format (standard image information format interlace nibble) of incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the interlace nibble that the interlacer receives in the image information control packet.

0x012C Reserved - - Reserved
0x0130 IMG_INFO_COLORSPACE - RO When you turn off lite mode and turn on Debug features, this register returns the color space that the interlacer derives from information in the image information control packet. Unused when you turn on lite mode.
0x0134 IMG_INFO_SUBSAMPLING - RO When you turn off lite mode and turn on Debug features, this register returns the subsampling that the interlacer derives from information in the image information control packet. Unused when you turn on lite mode.
0x0138 IMG_INFO_COSITING - RO When you turn off lite mode and turn on Debug features, this register returns the chroma siting that the interlacer derives from information in the image information control packet. Unused when you turn on lite mode.
0x013C IMG_INFO_FIELD_COUNT - RO When you turn off lite mode and turn on Debug features, this register returns the field count that the interlacer derives from information in the image information control packet. Unused when you turn on lite mode.
0x0138 to 0x013C unused
0x0140 STATUS RO

Bit 0: Status bit.

1 = interlacer is processing a video field, 0 otherwise.

Lite mode off only:

Bit 1: Pending register updates bit.

Any writes to the enable, ctrl_override or send_f1_first registers (0x0148 – 0x0150) cause the IP to raise the pending register updates bit, to indicate outstanding changes to the interlacer settings.

The IP lowers this bit at the next field boundary after a write to the COMMIT register.

0x0144 COMMIT RW Only used when you turn off lite mode. the IP holds any changes to the interlacer settings via the register map until a write is issued to this register. The value you write is unimportant.
0x0148 ENABLE RW Bit 0 of this register controls the creation of interlaced fields from progressive input. Set bit 0 to 0 to turn off interlacing and propagate progressive frames unaltered. Set bit 0 to 1 to turn on interlacing of progressive frames.
0x014C CTRL_OVERRIDE RW Bit 0 of this register controls override of the interlacing sequence by the interlaced nibble in the incoming image information packets (Lite mode off only). Set bit 1 of this register to 0 to turn off interlaced nibble override. Set bit 0 to 1 to turn on interlaced nibble override.
0x0150 SEND_F1_FIRST RW Bit 0 if this register controls whether an F0 or an F1 field is created first after any reset to the interlacing sequence. Set bit 0 to 0 to generate F0 first. Set bit 0 to 1 to generate F1 first.

Register Bit Descriptions

Table 451.   PROD_ID
Name Bits Description
Interlacer product ID 31:0 This register always returns 0x6AF7_0232.
Table 452.  VER
Name Bits Description
Register map version 7:0 Register map version. Returns 0x01.
Unused 15:8 Unused. Returns 0x04
QPDS minor revision 23:16 Updated for each release. For 22.2, returns 0x02
QPDS major revision 31:24 Updated for each release. For 22.2, returns 0x16.
Table 453.   LITE_MODE
Name Bits Description
Lite mode parameterization bit 31:0 Returns 1 if you turn on lite mode and 0 otherwise
Table 454.   DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 31:0 Returns 1 you turn on Debug features and 0 otherwise
Table 455.   IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

If lite mode is on, write to this register to set the expected width of the incoming video fields.

If lite mode is off and Debug features are on, this register returns the width-1 field from the most recently received image information packet and adds 1 to return a value for width.

unused 31:16 unused
Table 456.   IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

If lite mode is on, write to this register to set the expected height of the incoming video fields.

If lite mode is off and Debug features are on, this register reads the height-1 field from the most recently received image information packet and adds 1 to return a value for height.

unused 31:16 unused
Table 457.   IMG_INFO_INTERLACE
Name Bits Description
IntlaceNibble bits 3:0

If lite mode is on, write to this register to set the expected interlace format of the incoming video fields (interlace nibble).

If lite mode is off and Debug features are on, this register returns the intlaceNibble field from the most recently received image information packet.

unused 31:4 unused
Table 458.   IMG_INFO_COLORSPACE
Name Bits Description
CSP code bits 6:0

If lite mode is on, this register has no function.

If lite mode is off and Debug features are on, this register returns the 7 bit CSP field from the most recently received image information packet.

unused 31:7 unused
Table 459.   IMG_INFO_SUBSAMPLING
Name Bits Description
SubSa code bits 1:0

If lite mode is on, this register has no function.

If lite mode is off and Debug features are on, this register returns the SUBSA field from the most recently received image information packet.

unused 31:2 unused
Table 460.   IMG_INFO_COSITING
Name Bits Description
Cosite code bits 1:0

If lite mode is on, this register has no function.

If lite mode is off and Debug features are on, this register returns the COSITE field from the most recently received image information packet.

Unused 31:2 Unused
Table 461.   IMG_INFO_FIELD_COUNT
Name Bits Description
Count bits 6:0

If lite mode is on, this register has no function.

If lite mode is off and Debug features are on, this register returns the 7 bit FIELD_COUNT field from the most recently received image information packet.

Unused 31:7 Unused
Table 462.  STATUS
Name Bits Description
Status bit 0 1 = interlacer is processing a video field, 0 otherwise.
Pending register updates bit 1 1 = interlacer has pending updates, 0 otherwise
Unused 31:2 Unused
Table 463.  COMMIT
Name Bits Description
Unused 31:0 Unused
Table 464.  ENABLE
Name Bits Description
Interlacing enable 0 Set to 1 to turn on interlacing, set to 0 to turn off interlacing
Unused 31:1 Unused
Table 465.   CTRL_OVERRIDE
Name Bits Description
Interlace nibble override 0 Set to 1 to turn on interlace nibble override, set to 0 to turn off interlace nibble override
Unused 31:1 Unused
Table 466.  SEND_F1_FIRST
Name Bits Description
Send F1 first 0 Set to 1 to send F1 first after a reset to the interlacing sequence, set to 0 to send F0 first
Unused 31:1 Unused