Video and Vision Processing Suite Intel® FPGA IP User Guide
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Visible to Intel only — GUID: zxe1661431648882
Ixiasoft
Visible to Intel only — GUID: zxe1661431648882
Ixiasoft
32.3.2. Switch IP Interfaces
Name | Direction | Width | Description |
---|---|---|---|
Clocks and resets | |||
main_clock_clk | Input | 1 | AXI4-S processing clock. |
main_reset_rst | Input | 1 | AXI4-S processing reset. |
agent_clock_clk | Input | 1 | Optional control agent interface clock. |
agent_reset_reset | Input | 1 | Optional control agent interface reset. |
Control interfaces | |||
av_mm_control_agent_address | Input | 7 | Avalon memory-mapped agent address |
av_mm_control_agent_write | Input | 1 | Avalon memory-mapped agent write. |
av_mm_control_agent_writedata | Input | 32 | Avalon memory-mapped agent write data. |
av_mm_control_agent_byteenable | Input | 4 | Avalon memory-mapped agent byte enable. |
av_mm_control_agent_read | Input | 1 | Avalon memory-mapped agent read. |
av_mm_control_agent_readdata | Output | 32 | Avalon memory-mapped agent read data. |
av_mm_control_agent_readdatavalid | Output | 1 | Avalon memory-mapped agent read. |
av_mm_control_agent_waitrequest | Output | 1 | Avalon memory-mapped agent wait request. |
Intel FPGA streaming video interfaces Input interface number N (1 <= N < 8) |
|||
axi4s_vid_in_N_tdata | Input | 83 | AXI4-S data in. |
axi4s_vid_in_N_tvalid | Input | 1 | AXI4-S data valid. |
axi4s_vid_in_N_tuser[0] | Input | 1 | AXI4-S start of video frame. |
axi4s_vid_in_N_tuser[1] | Input | 1 | AXI4-S control or data packet. |
axi4s_vid_in_N_tuser[TUSERW-1:2] | Input | 84 | Unused. |
axi4s_vid_in_N_tlast | Input | 1 | AXI4-S end of packet. |
axi4s_vid_in_N_tready | Output | 1 | AXI4-S data ready. |
Output interface number M (1 <= M < 8) |
|||
axi4s_vid_out_M_tdata | Output | 83 | AXI4-S data in. |
axi4s_vid_out_M_tvalid | Output | 1 | AXI4-S data valid. |
axi4s_vid_out_M_tuser[0] | Output | 1 | AXI4-S start of video frame. |
axi4s_vid_out_M_tuser[1] | Output | 1 | AXI4-S control or data packet. |
axi4s_vid_out_M_tuser[TUSERW-1:2] | Output | 84 | Unused. |
axi4s_vid_out_M_tlast | Output | 1 | AXI4-S end of packet. |
axi4s_vid_out_M_tready | Input | 1 | AXI4-S data ready. |
The equation gives all tdata widths sizes in these interfaces:
max (floor(((bits per color sample x number of color planes x pixels in parallel)+ 7) / 8) x 8, 16)