Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide

19.2. FIR Filter Parameters

The IP offers run- and compile-time parameters.
Table 299.  FIR Filter Parameters
Parameter Values Description
Video Data Format
Input bits per color sample 8 to 16 Select the number of input bits per color sample.
Output bits per color sample 8 to 16 Select the number of output bits per color sample.
Number of color planes 1 to 4 Select the number of color planes per pixel.
Number of pixels in parallel 1 to 8 Select the number of pixels in parallel.
Video Blanking On or off Turn on when the filtered video has blanking
Maximum Frame Size
Maximum field height 2048-16384 Specify the maximum height of incoming frames
Maximum field width 2048-16384 Specify the maximum width of incoming frames
Filter Parameters
Vertical filter taps 3-16 Height of the FIR filter
Horizontal filter taps 3-16 Width of the FIR filter
Vertical kernel mirroring On or Off Turn on enable vertical symmetry
Horizontal kernel mirroring On or Off Turn on enable horizontal symmetry
Diagonal kernel mirroring On or Off Turn on diagonal symmetry
Rounding method Truncate, round half up or round half even Select the rounding method of choice for the output of the filter
Signed coefficients On or Off Turn on signed coefficients
Coefficient integer bits 0-18 Select the number of the coefficient’s integer bits. The sum of integer bits + fraction bits cannot exceed 18
Coefficient fraction bits 0-18 Select the number of the coefficient’s fraction bits. The sum of integer bits + fraction bits cannot exceed 18
Control Parameters
Memory-mapped control interface On or off Turn on for the Avalon memory-mapped control interface. You must have the Avalon memory-mapped control interface if you turn on Lite mode
Update Coefficients at runtime On or off Turn on run-time coefficient loading via the Avalon memory-mapped interface
Use memory initialization coefficients file On or off Turn on for a fixed coefficient file that the IP loads at compile time to assign coefficient values on reset.
Coefficients initialization file <file path> Specify the coefficients initialization file path
Figure 43. FIR Filter Parameters