Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
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10.1. About the Bits per Color Sample Adapter IP

The Intel FPGA Streaming Video protocol requires you to configure each interface for a maximum number of bits to represent each color sample. This setting determines the width of the tdata bus. The Bits per Color Sample Adapter IP allows you to connect two interfaces with different settings for bits per color sample.

When the input bits per color sample is less than the output bits per color sample, the IP adds the required number of bits at the LSB end of the tdata bus. The IP fixes these additional bits to 0. When the input bits per color sample is greater than the output bits per color sample, the IP clips the required number of bits from the LSB end of each color sample.

When you configure the IP for use with the lite variant of the Intel FPGA Streaming Video interface protocol, it consumes no FPGA resources as the clip and pad operations do not require any. However, when you configure the IP for use with the full variant of the protocol, a small amount of additional logic is required to ensure that the clip and pad operations do not affect the data in the nonvideo packets. The full variant of the protocol includes image information packets, and these packets contain a field indicating how many of the bits in each color plane are active for the current video stream.

When using the full variant of the protocol, you can include an Avalon Memory-mapped agent control interface to control the output bits per color field value at runtime via the register map. If you do not turn on Memory mapped control interface, the IP uses the default value for the bits per color field. When converting from a lower input bits per color sample value at the input to a higher value at the output, the IP does not modify this field as the pixel data does not change. However, when converting from a higher input bits per color sample value to a lower output bits per color sample value, you must modify the active bits per color sample field if it indicates a value greater than the maximum bits per color supported at the output.