Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
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25.4. Genlock Signal Router IP Registers

The IP allows runtime configuration of parameters via Avalon memory-mapped processor register interface.
Table 416.  Genlock Signal Router IP Registers
Offset Register Access Description
Parameterization registers
0x000 VID_PID RO Read this register to retrieve genlock signal router product ID. This register always returns 0x6FA7_0172.
0x004 VERSION_NUMBER RO Read this register to retrieve the version information for this IP.
0x008 PULSE_LENGTH RO Read this register to retrieve the number of clock cycles the start of frame pulse expects to be asserted high
0x00C Reserved RO
0x010 GENLOCK_INPUTS RO Read this register to retrieve the number of input ports
0x014 GENLOCK_OUTPUTS RO Read this register to retrieve the number of output ports
0x018 GENLOCK_OUTPUT_TYPE RO Read this register to retrieve the output type interface
0x01C – 0x098 INPUT_TYPE_{0 to 31} RO Read this register to retrieve the input type interface
Core Specific Registers
0x100 GPIO_INPUT RO Read this register to retrieve the data loaded in the general-purpose input register
0x104 GPIO_OUTPUT RW Read this register to retrieve the data loaded in the general-purpose output register. Alternatively, set this register to load a value into it.
0x180 OUTPUT_PORT_0 RW Sets the configuration parameters for output each of the output ports
0x184 OUTPUT_PORT_1 RW
0x188 OUTPUT_PORT_2 RW
0x18C OUTPUT_PORT_3 RW
0x190 OUTPUT_PORT_4 RW
0x194 OUTPUT_PORT_5 RW
0x198 OUTPUT_PORT_6 RW
0x19C OUTPUT_PORT_7 RW
0x1A0 OUTPUT_PORT_8 RW
0x1A4 OUTPUT_PORT_9 RW
0x1A8 OUTPUT_PORT_10 RW
0x1AC OUTPUT_PORT_11 RW
0x1B0 OUTPUT_PORT_12 RW
0x1B4 OUTPUT_PORT_13 RW
0x1B8 OUTPUT_PORT_14 RW
0x1BC OUTPUT_PORT_15 RW
0x1C0 OUTPUT_PORT_16 RW
0x1C4 OUTPUT_PORT_17 RW
0x1C8 OUTPUT_PORT_18 RW
0x1CC OUTPUT_PORT_19 RW
0x1D0 OUTPUT_PORT_20 RW
0x1D4 OUTPUT_PORT_21 RW
0x1D8 OUTPUT_PORT_22 RW
0x1DC OUTPUT_PORT_23 RW
0x1E0 OUTPUT_PORT_24 RW
0x1E4 OUTPUT_PORT_25 RW
0x1E8 OUTPUT_PORT_26 RW
0x1EC OUTPUT_PORT_27 RW
0x1E0 OUTPUT_PORT_28 RW
0x1F4 OUTPUT_PORT_29 RW
0x1F8 OUTPUT_PORT_30 RW
0x1FC OUTPUT_PORT_31 RW
Table 417.  Vid_pid
Bits Description
31:0 Product Identification Number
Table 418.  Version_number_pid
Bits Description
31:0 IP Version Number
Table 419.  Pulse_length
Bits Description
31:0 The number of clocks for the output genlock pulse
Table 420.  Genlock inputs
Bits Description
31:0 The number of input ports
Table 421.  Genlock output
Bits Description
31:0 The number of output ports
Table 422.  Genlock output type
Bits Description
31:0 Type of output interface
Table 423.  Input Type Nwhere N goes from 0 to 31
Bits Description
31:0 Type of input interface
Table 424.  GPIO Input
Bits Description
31:0 General-purpose input register
Table 425.  GPIO output
Bits Description
31:0 General-purpose output register
Table 426.  Output Port Nwhere N goes from 0 to 31
Bits Description
31 This field enables the output port
4:0 This field selects the input port to route to the output