Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
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16.5. Clocked Video Output IP Registers

The Clocked Video Output IP allows runtime configuration of parameters via Avalon memory-mapped processor register interface. The processor interface is optional. You turn it on at build time in the CVO Configuration GUI. Unless stated, all registers are 32-bit wide.

The address space is split into two regions. Addresses 0x140-0x194 are reserved for the core Clocked Video Output IP registers. Addresses 0x240-0x2FC are reserved for the optional internal Video Timing Generator. If you use the external AXI4-S full-raster input, registers 0x240-0x2FC are read only and return 0x1234abcd.

Table 220.   Parameterization Registers
Register Offset Access Description
Clocked Video Output Parameterization Registers
VID_PID 0x000 RO Read this register to retrieve clocked video output IP product ID
VERSION 0x004 RO Read this register to retrieve the version information for the Clocked Video Output IP
VID_FIFO_DEPTH 0x008 RO The depth of the video input cdc fifo.
TPG_FIFO_DEPTH 0x00c RO The depth of the test pattern input cdc fifo.
BPS 0x010 RO The bits per video sample
INTERNAL_VTIMING 0x014 RO

If ‘1’, the IP includes an internal video timing generator.

If ‘0’, and external video timing generator is required.

FALL_BACK_INPUT_EN 0x018 RO If ‘1’, the second video input has been enabled.
PIXELS_IN_PARALLEL 0x01c RO The number of pixels per clock transferred on the AXI4-S busses.
NUMBER_OF_COLOR_PLANES 0x020 RO The number of color planes per pixel
SEPARATE_SLAVE_CLOCK 0x024 RO This returns ‘1’ because the processor interface always uses a separate clock.
CPU_CLK_FREQ_HZ 0x028 RO The frequency, in Hz, of the processor interface clock.
TIM_DIMENSIONS 0x02c RO

If set to ‘1’, the processor Interface diagnostics include the dimensions of the input timing reference.

If 0, the dimensions of the timing reference are not available to the processor interface.

VID_IS_ASYNC 0x030 RO

If 1, the video input is treated as asynchronous to the timing reference.

If 0, the video input must use the AXI4-S full-raster video clock

VID_DIMENSIONS 0x034 RO

If 1, the processor interface diagnostics include the dimensions of the video input.

If 0, the dimensions of the video input are not available to the processor interface.

VID_DEBUG 0x038 RO

If 1, the processor Interface diagnostics include the locked, size err, and stall counters for the video input.

If 0, the counters are not available to the processor Interface

TPG_IS_ASYNC 0x03c RO

If 1, the test pattern input is treated as asynchronous to the timing reference.

If 0, the test pattern input must use the AXI4-S full-raster video clock

TPG_DIMENSIONS 0x040 RO

If 1, the processor interface diagnostics include the dimensions of the test pattern input.

If 0, the dimensions of the test pattern input are not available to the processor interface.

TPG_DEBUG 0x044 RO

If 1, the processor Interface diagnostics include the locked, size err, and stall counters for the test pattern input.

If 0, the counters are not available to the processor Interface

Video Timing Generator Parameterization Registers

These registers only exist if register 0x014 “INTERNAL_VTIMING” returns True.

NUM_PULSES 0x048 RO The number of additional output pulses generated by the internal Video Timing Generator.
HSIZE 0x04c RO The number of bits used to build the horizontal counters and comparators inside the Video Timing Generator. This determines the maximum width of raster that can be generated.
VSIZE 0x050 RO The number of bits used to build the vertical counters and comparators inside the Video Timing Generator. This determines the maximum height of raster that can be generated.
BUILD_HARD_FRAME_LOCK 0x054 RO

If true, the internal Video Timing Generator includes the Hard Frame Lock function.

If false, the internal Video Timing Generator cannot “hard lock” to an external reference.

BUILD_SOFT_FRAME_LOCK 0x058 RO

If true, the internal Video Timing Generator includes the Soft Frame Lock function.

If false, the internal Video Timing Generator cannot “soft lock” to an external reference.

BUILD_VRR 0x05c RO

If true, the internal Video Timing Generator includes the Variable Refresh Rate.

If false, the internal Video Timing Generator cannot generate a variable refresh rate.

Table 221.   Clocked Video Output Core Registers The core registers control the operation of the Clocked Video Output IP. They include optional diagnostic registers that assist with system development.
Register Offset Access Description
REG_STATUS 0x140 RO Returns the status of the merge process.
REG_BLACK_0 0x144 RW The initial value of “black” for this color plane
REG_BLACK_1 0x148 RW 35 The initial value of “black” for this color plane
REG_BLACK_2 0x14c RW 35 The initial value of “black” for this color plane
REG_BLACK_3 0x150 RW 35 The initial value of “black” for this color plane
REG_FALLBACK 0x154 RW Defines the behavior of the merge block if the video input fails
REG_FR_H_DIMS 0x158 RO 36 The active and total widths of the AXI4-S full-raster Timing Input
REG_FUR_V_DIMS 0x15c RO 36 The active and total heights of the AXI4-S full-raster Timing Input
REG_FR_FULL RASTEREQ_DIMS 0x160 RO 36 The frequency, in Hz, of the AXI4-S full-raster clock
REG_FR_CLKS_DIMS 0x164 RO36 The number of AXI4-S full-raster clocks per input frame.
REG_VID_DIMS 0x168 RO 36 The active height and width of the video input.
REG_VID_FREQ_DIMS 0x16c RO 36 The frequency, in Hz, of the video input clock
REG_VID_CLKS_DIMS 0x170 RO 36 The number of video input clocks per input frame.
REG_TPG_DIMS 0x174 RO 36 The active height and width of the test pattern input.
REG_TPG_FREQ_DIMS 0x178 RO 36 The frequency, in Hz, of the test pattern input clock
REG_TPG_CLKS_DIMS 0x17c RO 36 The number of test pattern input clocks per input frame.
REG_VID_LOCKED_COUNT 0x180 RO 36 Diagnostic counter that increments once at the start of each locked video frame.
REG_VID_SIZE_ERR_COUNT 0x184 RO 36 Diagnostic counter that increments every time a mismatch between the video input and timing input is detected.
REG_VID_STALL_COUNT 0x188 RO 36 Diagnostic counter that increments every time the video input stalls and is dropped by the merge block.
REG_TPG_LOCKED_COUNT 0x18c RO 36 Diagnostic counter that increments once at the start of each locked test pattern frame.
REG_TPG_SIZE_ERR_COUNT 0x190 RO 36 Diagnostic counter that increments every time a mismatch between the test pattern input and timing input is detected.
REG_TPG_STALL_COUNT 0x194 RO 36 Diagnostic counter that increments every time the test pattern input stalls and is dropped by the merge block.

Register Bit Descriptions

Table 222.  REG_STATUS
Name Bits Attribute Description
VID_LOCKED 0 RO

When ‘1’, the video input is locked with the timing reference

When ‘0’, the IP is waiting to achieve “lock” between the video input and the timing reference.

VID_AXI4-S_FULL 1 RO

When ‘1’, the IP has detected the video input is an AXI4-S Full stream

When ‘0’, the IP has detected the video input is an AXI4-S Lite stream

VID_STALL_ERR 2 RO

When ‘1’, the video input has stalled (dropped it’s tValid) when the timing reference has required active pixels.

When ‘0’, the video input is supplying pixels at the required pixel rate.

VID_SIZE_ERR 3 RO

When ‘1’, the active dimensions of the video input do not match the active dimensions of the timing reference.

When ‘0’, the active dimensions of the video input and the timing reference match.

TPG_LOCKED 4 RO

When ‘1’, the test pattern input is locked with the timing reference

When ‘0’, the IP is waiting to achieve “lock” between the test pattern input and the timing reference.

TPG_AXI4-S_FULL 5 RO

When ‘1’, the IP has detected the test pattern input is an AXI4-S Full stream

When ‘0’, the IP has detected the test pattern input is an AXI4-S Lite stream

TPG_STALL_ERR 6 RO

When ‘1’, the test pattern input has stalled (dropped it’s tValid) when the timing reference has required active pixels.

When ‘0’, the test pattern input is supplying pixels at the required pixel rate.

TPG_SIZE_ERR 7 RO

When ‘1’, the active dimensions of the test pattern input do not match the active dimensions of the timing reference.

When ‘0’, the active dimensions of the test pattern input and the timing reference match.

TIMING_PHASE 11:8 RO If there are 2 or more Pixels in Parallel, this indicates where the first active pixel occurred for the current line.
Reserved 31:12 Rsvd Reserved
Table 223.  REG_BLACK_0
Name Bits Attribute Description
BLACK_0 BIT_DEPTH-1:0 RW The initial value of “black” for this color plane
Table 224.  REG_BLACK_1
Name Bits Attribute Description
BLACK_1 BIT_DEPTH-1:0 RW

The initial value of “black” for this color plane

This register is RO and returns 0x1234abcd if the color plane does not exist

Table 225.  REG_BLACK_2
Name Bits Attribute Description
BLACK_2 BIT_DEPTH-1:0 RW

The initial value of “black” for this color plane

This register is RO and returns 0x1234abcd if the color plane does not exist

Table 226.  REG_BLACK_3
Name Bits Attribute Description
BLACK_3 BIT_DEPTH-1:0 RW

The initial value of “black” for this color plane

This register is RO and returns 0x1234abcd if the color plane does not exist

Table 227.  REG_FALLBACK
Name Bits Attribute Description
Auto Recover 0 RW

If the input video is dropped due to an error, then when this bit is ‘1’ the IP automatically returns to the video input once it is relocked

If ‘0’, the IP does not automatically return to the video input following an error, and you must manually switch using the “recover now” register bit.

Force Black 1 RW If ‘1’, the IP is forced to output the Clocked Video Output IP Black values.
Force TPG 2 RW If ‘1’, the IP is forced to output the Test Pattern video input.
Force Video 3 RW If ‘1’, the IP is forced to output the video input.
Reserved 30:4 Rsvd Reserved
Recover Now 31 W1R0

This register bit self-clears.

Write a ‘1’ to this bit to force the IP to return to the video input if the video input is valid.

Writing a ‘0’ has no effect.

Table 228.  REG_FR_H_DIMS
Name Bits Attribute Description
hTotal 15:0 RO Returns the detected total width of the timing reference.
hActive 31:16 RO Returns the detected active width of the timing reference.
Table 229.  REG_FR_V_DIMS
Name Bits Attribute Description
vTotal 15:0 RO Returns the detected total height of the timing reference.
vActive 31:16 RO Returns the detected active height of the timing reference.
Table 230.  REG_FR_FREQ_DIMS
Name Bits Attribute Description
Clock Frequency 31:0 RO The frequency, in Hz, of the AXI4-S full-raster clock
Table 231.  REG_FR_CLKS_DIMS
Name Bits Attribute Description
Frame Period 31:0 RO The number of AXI4-S full-raster clocks per input frame.
Table 232.   REG_VID_DIMS
Name Bits Attribute Description
hActive 15:0 RO The detected active with of the video input.
vActive 31:16 RO The detected active height of the video input
Table 233.  REG_VID_FREQ_DIMS
Name Bits Attribute Description
Clock Frequency 31:0 RO The frequency, in Hz, of the video input clock
Table 234.  REG_VID_CLKS_DIMS
Name Bits Attribute Description
Frame Period 31:0 RO The number of video input clocks per input frame.
Table 235.   REG_TPG_DIMS
Name Bits Attribute Description
hActive 15:0 RO The detected active with of the test pattern input.
vActive 31:16 RO The detected active height of the test pattern input
Table 236.  REG_TPG_FREQ_DIMS
Name Bits Attribute Description
Clock Frequency 31:0 RO The frequency, in Hz, of the test pattern input clock
Table 237.  REG_TPG_CLKS_DIMS
Name Bits Attribute Description
Frame Period 31:0 RO The number of test pattern input clocks per input frame.
Table 238.  REG_VID_LOCKED_COUNT
Name Bits Attribute Description
Locked Count 31:0 RO Diagnostic counter that increments once at the start of each locked video frame.
Table 239.  REG_VID_SIZE_ERR_COUNT
Name Bits Attribute Description
Size Error Count 31:0 RO Diagnostic counter that increments every time a mismatch between the video input and timing input is detected.
Table 240.  REG_VID_STALL_COUNT
Name Bits Attribute Description
Stall Count 31:0 RO Diagnostic counter that increments every time the video input stalls and is dropped by the merge block.
Table 241.  REG_TPG_LOCKED_COUNT
Name Bits Attribute Description
Locked Count 31:0 RO Diagnostic counter that increments once at the start of each locked test pattern input frame.
Table 242.  REG_TPG_SIZE_ERR_COUNT
Name Bits Attribute Description
Size Error Count 31:0 RO Diagnostic counter that increments every time a mismatch between the test pattern input and timing input is detected.
Table 243.  REG_TPG_STALL_COUNT
Name Bits Attribute Description
Stall Count 31:0 RO Diagnostic counter that increments every time the test pattern input stalls and is dropped by the merge block.

Video Timing Generator Registers

The Clocked Video Output IP includes an optional internal Video Timing Generator IP. The Video Timing Generator IP processor registers start at address offset 0x240.

The offset to the Video Timing Generator IP registers is different when you use them in the Clocked Video Output IP, compared to standalone.

Table 244.  Video Timing Generator Registers
Register Offset Access Description

Raster Timing Registers

REG_STATUS 0x240 RO Reserved
REG_COMMIT 0x244 RW Update internal parameters with new video standard.
REG_MODE 0x248 RW Control mode of operation.
REG_RESET_POS 0x24c RW Expected position of the start of frame input signal, relative to the raster
REG_TOTALS 0x250 RW Total height and width of the raster
REG_HB_END 0x254 RW First active pixel of a line
REG_V1B_POS 0x258 RW Start and end of vertical blanking for field 1
REG_V2B_POS 0x25c RW Start and end of vertical blanking for field 2
REG_FIELD_STARTS 0x260 RW First lines of field 1 and 2
REG_HS_POS 0x264 RW The start and end of horizontal sync
REG_V1S_START 0x268 RW The horizontal and vertical position of the start of the vertical sync for field 1
REG_V1S_END 0x26c RW The horizontal and vertical position of the end of the vertical sync for field 1
REG_V2S_START 0x270 RW The horizontal and vertical position of the start of the vertical sync for field 2
REG_V2S_END 0x274 RW The horizontal and vertical position of the end of the vertical sync for field 2
REG_JITTER_CONT 0x278 RW Timing parameters for the hard and soft frame lock
REG_BLACK_0 0x27c RW The initial value of “black” for this color plane
REG_BLACK_1 0x280 RW35 The initial value of “black” for this color plane
REG_BLACK_2 0x284 RW35 The initial value of “black” for this color plane
REG_BLACK_3 0x288 RW35 The initial value of “black” for this color plane
REG_FRAME_COUNTS 0x28c RO Returns the total number of frames output, and the number of external frame starts received.
REG_FRAME_LENGTH 0x290 RO The number of video clocks between consecutive frame start input signals
REG_VTOTAL_ADJ 0x294 RO37 The total height of the raster after adjustment for soft Lock.
REG_VID_FREQ 0x298 RO The frequency of the video clock, in Hz.
REG_GENLOCK_STATS0 0x29c RO Diagnostics for hard and soft frame lock
REG_GENLOCK_STATS1 0x2a0 RO Diagnostics for Soft frame lock.

Pulse and Toggle Timing Registers

REG_PULSE0_START 0x2c0 RW 38 The horizontal and vertical position of the start of the pulse
REG_PULSE0_END 0x2c4 RW 38 The horizontal and vertical position of the end of the pulse
REG_PULSE1_START 0x2c8 RW38 The horizontal and vertical position of the start of the pulse
REG_PULSE1_END 0x2cc RW38 The horizontal and vertical position of the end of the pulse
REG_PULSE2_START 0x2d0 RW38 The horizontal and vertical position of the start of the pulse
REG_PULSE2_END 0x2d4 RW38 The horizontal and vertical position of the end of the pulse
REG_PULSE3_START 0x2d8 RW38 The horizontal and vertical position of the start of the pulse
REG_PULSE3_END 0x2dc RW38 The horizontal and vertical position of the end of the pulse
REG_PULSE4_START 0x2e0 RW38 The horizontal and vertical position of the start of the pulse
REG_PULSE4_END 0x2e4 RW38 The horizontal and vertical position of the end of the pulse
REG_PULSE5_START 0x2e8 RW38 The horizontal and vertical position of the start of the pulse
REG_PULSE5_END 0x2ec RW38 The horizontal and vertical position of the end of the pulse
REG_PULSE6_START 0x2f0 RW38 The horizontal and vertical position of the start of the pulse
REG_PULSE6_END 0x2f4 RW38 The horizontal and vertical position of the end of the pulse
REG_PULSE7_START 0x2f8 RW38 The horizontal and vertical position of the start of the pulse
REG_PULSE7_END 0x2fc RW38 The horizontal and vertical position of the end of the pulse
35

This register is RO and returns 0x1234abcd if the color plane does not exist

36

This register is optional. If turned off on the CVO Configuration GUI, this register returns 0x1234abcd

37

If Soft Mode is turned off, this register is undefined.

38

This register is RO and returns 0x1234abcd if the pulse does not exist. Refer to the Number of pulses parameter.