Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
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40.5. Video Timing Generator IP Registers

The processor interface is optional. You must turn it on at build time on the Build Parameters tab in the GUI. Unless stated, all registers are 32-bit wide.
Table 788.  External Processor Interface

The Video Timing Generator IP allows run-time configuration of parameters via an Avalon memory-mapped processor register interface.

Register Offset Access Description

Parameterization Registers

VID_PID 0x000 RO Read this register to retrieve the product ID
VERSION 0x004 RO Read this register to retrieve the version information for the IP.
NUM_PULSES 0x008 RO The number of additional output pulses generated by the Video Timing Generator.
OUTPUT_IS_CV 0x00c RO

When 1, the output is legacy Intel Clocked Video.

When 0, the output is a full-raster variant.

ALIGNED_ONLY 0x010 RO

When 1, the raster is restricted such that all timing parameters for the raster must be integer multiples of the number of pixels in parallel.

When 0, the timing parameters have no restrictions.

NUMBER_OF_COLOR_PLANES 0x014 RO The number of color planes per pixel.
PIXELS_IN_PARALLEL 0x018 RO The number of pixels per clock transferred on the AXI4-S buses.
BPS 0x01c RO The bits per video sample.
HSIZE 0x020 RO The number of bits to build the horizontal counters and comparators in the Video Timing Generator. Determines the maximum width of raster that the IP can generate.
VSIZE 0x024 RO The number of bits to build the vertical counters and comparators inside the Video Timing Generator. Determines the maximum height of raster that the IP can generate.
CPU_CLK_FREQ_HZ 0x028 RO The frequency, in Hz, of the processor interface clock.
BUILD_HARD_FRAME_LOCK 0x02c RO

If true, the Video Timing Generator includes the hard frame lock function.

If false, the Video Timing Generator cannot achieve a hard lock to an external reference.

BUILD_SOFT_FRAME_LOCK 0x030 RO

If true, the Video Timing Generator includes the soft frame lock function.

If false, the Video Timing Generator cannot achieve a soft lock to an external reference.

BUILD_VRR 0x034 RO

If true, the Video Timing Generator includes the variable refresh rate.

If false, the Video Timing Generator cannot generate a variable refresh rate.

Table 789.  Core Processor Register Description
Register Offset Access Description

Raster Timing Registers

REG_STATUS 0x140 RO Reserved
REG_COMMIT 0x144 RW Update internal parameters with new video standard.
REG_MODE 0x148 RW Control mode of operation.
REG_RESET_POS 0x14c RW Expected position of the start of frame input signal, relative to the raster
REG_TOTALS 0x150 RW Total height and width of the raster
REG_HB_END 0x154 RW First active pixel of a line
REG_V1B_POS 0x158 RW Start and end of vertical blanking for field 1
REG_V2B_POS 0x15c RW Start and end of vertical blanking for field 2
REG_FIELD_STARTS 0x160 RW First lines of field 1 and 2
REG_HS_POS 0x164 RW The start and end of horizontal sync
REG_V1S_START 0x168 RW The horizontal and vertical position of the start of the vertical sync for field 1
REG_V1S_END 0x16c RW The horizontal and vertical position of the end of the vertical sync for field 1
REG_V2S_START 0x170 RW The horizontal and vertical position of the start of the vertical sync for field 2
REG_V2S_END 0x174 RW The horizontal and vertical position of the end of the vertical sync for field 2
REG_JITTER_CONT 0x178 RW Timing parameters for the hard and soft frame locks
REG_BLACK_0 0x17c RW The initial value of black for this color plane
REG_BLACK_1 0x180 RW 116 The initial value of black for this color plane
REG_BLACK_2 0x184 RW 116 The initial value of black for this color plane
REG_BLACK_3 0x188 RW 116 The initial value of black for this color plane
REG_FRAME_COUNTS 0x18c RO Returns the total number of frames output, and the number of external frame starts received.
REG_FRAME_LENGTH 0x190 RO The number of video clocks between consecutive frame start input signals
REG_VTOTAL_ADJ 0x194 RO 117 The total height of the raster after adjustment for soft frame lock.
REG_VID_FREQ 0x198 RO The frequency of the video clock, in Hz.
REG_GENLOCK_STATS0 0x19c RO Diagnostics for hard and soft frame lock
REG_GENLOCK_STATS1 0x1a0 RO Diagnostics for soft frame lock.

Pulse and Toggle Timing Registers

REG_PULSE0_START 0x1c0 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE0_END 0x1c4 RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE1_START 0x1c8 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE1_END 0x1cc RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE2_START 0x1d0 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE2_END 0x1d4 RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE3_START 0x1d8 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE3_END 0x1dc RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE4_START 0x1e0 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE4_END 0x1e4 RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE5_START 0x1e8 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE5_END 0x1ec RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE6_START 0x1f0 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE6_END 0x1f4 RW 118 The horizontal and vertical position of the end of the pulse
REG_PULSE7_START 0x1f8 RW 118 The horizontal and vertical position of the start of the pulse
REG_PULSE7_END 0x1fc RW 118 The horizontal and vertical position of the end of the pulse
Table 790.  REG_STATUS
Name Bits Attribute Description
Reserved 31:0 Rsvd Reserved
Table 791.  REG_COMMIT
Name Bits Attribute Description
Commit 0 WO Writing a 1 to this bit causes all uploaded processor parameters to be committed to the Video Timing Generators at the start of the next raster.
VidClkRunning 1 RO

1 indicates the video clock is running.

0 indicates the video clock is not running, or is unstable.

UpdateTimingRequest 2 RO

1 indicates the IP issues a commit, but is not completed. Ther commit logic has seen no start of raster.

0 indicates no commit is pending.

Table 792.  REG_MODE
Name Bits Attribute Description
Frame Start is Pulse 0 RW

Sets the type of signal for the frame start input

If 1, the input is a short pulse

If 0, the input is a per-frame toggle

Blank_n_Sync 1 RW

If 1, the IP generates blank timing

If 0, the IP generates sync timing

HardFrameLock 2 RW

If 1, the soft frame lock is false.

If 0, the soft frame lock is true

SoftFrameLock 3 RW

If 1, and the soft frame lock is false, soft frame lock is on.

If 0, soft frame lock is off.

VRR Enable 4 RW

If 1, variable refresh rate is on.

If 0, variable refresh rate is off.

VRR Line Mode 5 RW

If variable refresh rate is on, set to 1 to turn on the VVR Line Mode.

If set to 0, VVR Line Mode is off.

Reserved 31:6 RO Reserved
Table 793.  REG_RESET_POS
Name Bits Attribute Description
hReset hSize-1:0 RW The horizontal position, in pixels, of the expected frame start input signal
vReset 15+vSize:16 RW The vertical position, in lines, of the expected frame start input signal
Table 794.  REG_TOTALS
Name Bits Attribute Description
hTotal hSize-1:0 RW The width, in pixels, of the raster
vTotal 15+vSize:16 RW The height, in lines, of the raster
Table 795.  REG_HB_END
Name Bits Attribute Description
HB_END hSize-1:0 RW The first active pixel after the horizontal blanking.
Reserved 32:hSize RO Reserved
Table 796.  REG_V1B_POS
Name Bits Attribute Description
V1B Start vSize-1:0 RW The first line of vertical blanking for field 1
V1B End 15+vSize:16 RW The first active line of field 1
Table 797.  REG_V2B_POS
Name Bits Attribute Description
V2B Start vSize-1:0 RW

The first line of vertical blanking for field 2

For a progressive raster, set to -1

V2B End 15+vSize:16 RW

The first active line of field2

For a progressive raster, set to -1

Table 798.  REG_FIELD_STARTS
Name Bits Attribute Description
Field 1 Start vSize-1:0 RW The first line of field 1
Field 2 End 15+vSize:16 RW

The first line of field 2

For a progressive raster, set to -1

Table 799.  REG_HS_POS
Name Bits Attribute Description
HSync Start hSize-1:0 RW The first pixel of the horizontal sync
HSync End 15+hSize:16 RW The first pixel after the horizontal sync
Table 800.  REG_V1S_START
Name Bits Attribute Description
V1Sync hStart hSize-1:0 RW The first pixel of the vertical sync for field 1
V1Sync vStart 15+hSize:16 RW The first line of the vertical sync for field 1
Table 801.  REG_V1S_END
Name Bits Attribute Description
V1Sync hEnd hSize-1:0 RW The first pixel after the vertical sync for field 1
V1Sync vEnd 15+hSize:16 RW The last line of the vertical sync for field 1
Table 802.  REG_V2S_START
Name Bits Attribute Description
V2Sync hStart hSize-1:0 RW

The first pixel of the vertical sync for field 2

For a progressive raster, set to -1

V2Sync vStart 15+hSize:16 RW

The first line of the vertical sync for field 2

For a progressive raster, set to -1

Table 803.  REG_V2S_END
Name Bits Attribute Description
V2Sync hEnd hSize-1:0 RW

The first pixel after the vertical sync for field 2

For a progressive raster, set to -1

V2Sync vEnd 15+vSize:16 RW

The last line of the vertical sync for field 2

For a progressive raster, set to -1

Table 804.  REG_JITTER_CONT
Name Bits Attribute Description
Frame Start Max Jitter 7:0 RW

The number of video clock cycles either side of the position of the expected start of frame where an occurrence of the frame start input signal does not cause the raster to restart.

If the frame start input signal occurs more than this number of video clock cycles from the point where it is expected, the IP restarts the output raster.

Soft lock frame start ignore 15:8 RW

When you select True for Soft frame lock, this parameter specifies the number of lines where the frame start input signal is ignored.

When you select True for Soft frame lock, this parameter is not used.

Soft lock frame start adjust 23:16 RW

When you select True for Soft frame lock, this parameter specifies the total number of lines for soft lock, including the ignore lines.

When you select False for Soft frame lock, this parameter is not used.

Reserved 31:24 RO Reserved
Table 805.  REG_BLACK_0
Name Bits Attribute Description
BLACK_0 BIT_DEPTH-1:0 RW The initial value of black for this color plane
Table 806.  REG_BLACK_1
Name Bits Attribute Description
BLACK_1 BIT_DEPTH-1:0 RW

The initial value of black for this color plane

This register is RO and returns 0x1234abcd if the color plane does not exist

Table 807.  REG_BLACK_2
Name Bits Attribute Description
BLACK_2 BIT_DEPTH-1:0 RW

The initial value of black for this color plane

This register is RO and returns 0x1234abcd if the color plane does not exist

Table 808.  REG_BLACK_3
Name Bits Attribute Description
BLACK_3 BIT_DEPTH-1:0 RW

The initial value of black for this color plane

This register is RO and returns 0x1234abcd if the color plane does not exist

Table 809.  REG_FRAME_COUNTS
Name Bits Attribute Description
Start Counter 15:0 RO Counts occurrences of the Frame Start Input Signal.
Frame Counter 31:16 RO Counts number of frames generated.
Table 810.  REG_FRAME_LENGTH
Name Bits Attribute Description
Frame Length hSize+vSize-1:0 RO The number of video clocks per occurrence of the frame start input signal.
Table 811.  REG_VTOTAL_ADJ
Name Bits Attribute Description
vTotal_Adj vSize-1:0 RO The total number of lines per frame used by the soft frame lock.
Reserved 31:vSize RO Reserved.
Table 812.  REG_VID_FREQ
Name Bits Attribute Description
VidClkFreq 31:0 RO The frequency of the video clock, in Hz.
Table 813.  REG_GENLOCK_STATS0
Name Bits Attribute Description
Reset Count 15:0 RO

Counts the number of times the raster is reset by the frame start signal.

Normally static and only increments when the output standard is changed. If this value is constantly incrementing, it suggests the period of the frame start signal does not match the period of the output raster.

Stable Count 31:16 RO This increments every time the soft frame lock mechanism does not change the vTotal_adj value.
Table 814.   REG_GENLOCK_STATS1
Name Bits Attribute Description
vTotal Inc Counter 15:0 RO Increments every time the soft frame lock mechanism increments the vTotal_adj value.
vTotal Dec Counter 31:16 RO Increments every time the soft frame lock mechanism decrements the vTotal_adj value.
Table 815.  REG_PULSE0_START
Name Bits Attribute Description
Pulse 0 hStart hSize-1:0 RW

The first pixel of the pulse

Pulse 0 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 816.  REG_PULSE0_END
Name Bits Attribute Description
Pulse 0 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 0 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 817.  REG_PULSE1_START
Name Bits Attribute Description
Pulse 1 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 1 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 818.  REG_PULSE1_END
Name Bits Attribute Description
Pulse 1 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 1 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 819.  REG_PULSE2_START
Name Bits Attribute Description
Pulse 2 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 2 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 820.  REG_PULSE2_END
Name Bits Attribute Description
Pulse 2 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 2 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 821.  REG_PULSE3_START
Name Bits Attribute Description
Pulse 3 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 3 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 822.  REG_PULSE3_END
Name Bits Attribute Description
Pulse 3 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 3 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 823.  REG_PULSE4_START
Name Bits Attribute Description
Pulse 4 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 4 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 824.  REG_PULSE4_END
Name Bits Attribute Description
Pulse 4 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 4 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 825.   REG_PULSE5_START
Name Bits Attribute Description
Pulse 5 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 5 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 826.  REG_PULSE5_END
Name Bits Attribute Description
Pulse 5 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 5 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 827.  REG_PULSE6_START
Name Bits Attribute Description
Pulse 6 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 6 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 828.  REG_PULSE6_END
Name Bits Attribute Description
Pulse 6 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 6 vEnd 15+vSize:16 RW

The last line of the pulse.

119
Table 829.  REG_PULSE7_START
Name Bits Attribute Description
Pulse 7 hStart hSize-1:0 RW

The first pixel of the pulse

119
Pulse 7 vStart 15+vSize:16 RW

The first line of the pulse

119
Table 830.  REG_PULSE7_END
Name Bits Attribute Description
Pulse 7 hEnd hSize-1:0 RW

The last pixel of the pulse.

119
Pulse 7 vEnd 15+vSize:16 RW

The last line of the pulse.

119
116

This register is RO and returns 0x1234abcd if the color plane does not exist.

117

If Soft Mode is off, this register is undefined.

118

This register is RO and returns 0x1234abcd if the pulse does not exist. Refer to Build Parameter tab Number of pulses

119

This register is RO and returns 0x1234abcd if the pulse does not exist. Refer to the Build Parameter tab Number of pulses