Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide

13.4. Clipper IP Registers

Table 141.   Control Registers In the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_CLIPPER as appropriate and with an optional REG suffix
Address Register Access Description
Lite 19 Full
Parameterization registers
0x0000 VID_PID RO RO

Read this register for the clipper product ID.

This register always returns 0x6AF7_022D.

0x0004 VERSION RO RO

Read this register for the version information for the clipper.

0x0008 LITE_MODE RO RO

Read this register to determine if Lite mode is on or off.

This register returns 0 when Lite mode is off and 1 when on.

0x000C DEBUG_ENABLED RO RO

Read this register to determine if Debug features is on.

0x0010 CLIPPING_MODE RO RO Read this register to determine the Clipping method
0x0014 to 0x011F Unused.
Control and debug registers 20
0x0120 IMG_INFO_WIDTH RW RO For lite designs, the expected width of the incoming video fields. For full, the received width in the IP derives from the image information packets.
0x0124 IMG_INFO_HEIGHT RW RO For lite designs, the expected height of the incoming video fields. For full the received height in the IP derives from the image information packets.
0x0128 IMG_INFO_INTERLACE RW RO For lite designs, the expected interlace information of the incoming video fields. For full, the received interlace information in image information packets.
0x012C Reserved - - Reserved.
0x0130 IMG_INFO_COLORSPACE RW RO For lite designs, the expected color space of the incoming video fields. For full, the received color space in image information packets.
0x0134 IMG_INFO_SUBSAMPLING RW RO For lite designs, the expected chroma subsampling of the incoming video fields. For full, the received chroma subsampling in image information packets.
0x0138 IMG_INFO_COSITING RW RO For lite designs, the expected chroma co-siting of the incoming video fields. For full, the received chroma co-siting in image information packets.
0x013C IMG_INFO_FIELD_COUNT - RO The received field count field in image information packets.
0x0140 STATUS RO RO

Bit 0: status bit.

1 = clipper is processing a video field, 0 otherwise.

Full designs only:

Bit 1: Pending register updates bit.

Any writes to the clipping specification registers (0x0148 - 0x0154) cause the pending register updates bit to be raised, to indicate outstanding changes to the clipping settings.

The IP lowers this bit at the start of the first packet for a new frame (first packet after the EOP packet) after a write to the COMMIT register.

0x0144 COMMIT RW RW

The IP uses this register with the STATUS register pending register updates bit.

Write any value to this register after writing new values to any of the clipping specification registers (0x0148 - 0x0154). The clipper switches to the new clipping specification values at the start of the next video frame after you write to this register.

The commit register ensures atomic register updates, avoiding the IP only applying some of the updated register values for the next incoming frame.

Clipping specification registers
0x0148 LEFT_OFFSET RW RW

If you select Clipping with offsets, write to this register to set the required offset from the left edge of the video.

If you select Clipping with output dimensions, this offset defines the offset from the left edge of the video for top left corner of the clipped output.

0x014C TOP_OFFSET RW RW

If you select Clipping with offsets, write to this register to set the required offset from the top edge of the video.

If you select Clipping with output dimensions, this offset defines the offset from the top edge of the video for the top left corner of the clipped output.

0x0150 RIGHT_OFFSET/CLIP_WIDTH RW RW

If you select Clipping with offsets, write to this register to set the required offset from the right edge of the video.

If you select Clipping with output dimensions, write to this register to set the required width of the output video.

0x0154

BOTTOM_OFFSET/CLIP_HEIGHT

RW RW

If you select Clipping with offsets, write to this register to set the required offset from the bottom edge of the video.

If you select Clipping with output dimensions, write to this register to set the required height of the output video.

Register Bit Descriptions

Table 142.   VID_PID
Name Bits Description
Clipper version ID and product ID 31:0 This register always returns 0x6AF7_022D.
  • 15:0 is the product ID and always returns 0x022D
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 143.   VERSION
Name Bits Description
Lite mode parameterization bit 7:0 Register map version. Returns 0x01.
QPDS patch revision 15:8 Returns 0x00
QPDS update revision 23:16 Updated for each release. For 21.4, returns 0x04
QPDS major revision 31:24 Updated for each release. For 21.4, returns 0x15.
Table 144.   LITE_MODE
Name Bits Description
Lite mode parameterization bit 0 Returns 1 if you turn on lite mode.
Unused 31:1 Unused.
Table 145.   DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 0 Returns 1 if you turn on Debug features.
Unused 31:1 Unused.
Table 146.   CLIPPING_MODE
Name Bits Description
Clipping mode bit 0 This bit is 0 if you select Clipping with offsets and 1 if you select Clipping with output dimensions.
Unused 31:1 Unused.
Table 147.   IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

When you turn on Lite mode, write to this register to set the expected width of the incoming video fields.

When you turn off Lite mode and turn on Debug features, this register returns the width-1 field from the most recently received image information packet and adds 1 to return a value for width.

unused 31:16 Unused.
Table 148.   IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

When you turn on Lite mode, write to this register to set the expected height of the incoming video fields.

When you turn off Lite mode and turn on Debug features, this register returns the height-1 field from the most recently received image information packet and adds 1 to return a value for height.

unused 31:16 Unused.
Table 149.   IMG_INFO_INTERLACE
Name Bits Description
IntlaceNibble bits 3:0

When you turn on Lite mode, write to this register to set the expected interlacing of the incoming video fields.

When you turn off Lite mode and turn on Debug features, this register returns the intlaceNibble field from the most recently received image information packet.

unused 31:4 Unused.
Table 150.   IMG_INFO_COLORSPACE
Name Bits Description
CSP code bits 6:0

When you turn on Lite mode, write to this register to set the expected color space of the incoming video fields.

When you turn off Lite mode and turn on Debug features, this register returns the 7 bit CSP field from the most recently received image information packet.

unused 31:7 Unused.
Table 151.   IMG_INFO_SUBSAMPLING
Name Bits Description
CSPSubSa code bits 1:0

When you turn on Lite mode, write to this register to set the expected chroma subsampling of the incoming video fields.

When you turn off Lite mode and turn on Debug features, this register returns the SUBSA field from the most recently received image information packet.

unused 31:2 Unused.
Table 152.   IMG_INFO_COSITING
Name Bits Description
Cosite code bits 1:0

When you turn on Lite mode, write to this register to set the expected chroma co-siting of the incoming video fields.

When you turn off Lite mode and turn on Debug features, this register returns the COSITE field from the most recently received image information packet.

unused 31:2 Unused.
Table 153.   IMG_INFO_FIELD_COUNT
Name Bits Description
Count bits 6:0

When you turn on Lite mode, this register has no function.

When you turn off Lite mode and turn on Debug features, this register returns the 7 bit FIELD_COUNT field from the most recently received image information packet.

unused 31:7 Unused.
Table 154.   STATUS
Name Bits Description
Status bit 0 1 = clipper is processing a video field, 0 otherwise.
Pending register updates bit 1 1 = clipper has pending updates, 0 otherwise
Table 155.   COMMIT
Name Bits Description
Commit bits 31:0 Write to any bits to trigger a commit.
Table 156.   LEFT_OFFSET
Name Bits Description
Left offset 15:0 If you select Clipping with offsets in the GUI, write to this register to set the required offset from the left edge of the video.
Table 157.   TOP_OFFSET
Name Bits Description
Top offset 15:0 If you select Clipping with offsets in the GUI, write to this register to set the required offset from the top edge of the video.
Table 158.   RIGHT_OFFSET_ REG/CLIP_WIDTH
Name Bits Description
Offset or width 15:0

If you select Clipping with offsets in the GUI, write to this register to set the required offset from the right edge of the video.

If you select Clipping with output dimensions in the GUI, write to this register to set the required width of the output video.

Table 159.   BOTTOM_OFFSET/CLIP_HEIGHT
Name Bits Description
Offset or height 15:0

If you select Clipping with offsets in the GUI, write to this register to set the required offset from the bottom edge of the video.

If you select Clipping with output dimensions in the GUI, write to this register to set the required height of the output video.

19

When you turn on lite mode, registers are RW only if you turn on Debug features, otherwise they are WO. For full, turn off lite mode.

20

For more details of these registers, refer to Control Packets