Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
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11.5. Chroma Key IP Registers

Each register is either read-only (RO) or read-write (RW).

In the software API the register names appear with a prefix of INTEL_VVP,INTEL_VVP_CORE, or INTEL_VVP_CHROMA_KEY as appropriate and with an optional REGsuffix.

Table 83.   Control Registers
Address Register Access Description
Lite 12 Full
Parameterization registers
0x0000 PROD_ID RO RO Read this register for the Chroma Key product ID. This register always returns 0x6AF7_023F.
0x0004 VER RO RO Read this register to retrieve the version information for the Chroma Key.
0x0008 LITE_MODE RO RO

Read this register to determine if Lite mode is on or off.

This register returns 0 when Lite mode is off and 1 when on.

0x000C DEBUG_ENABLED RO RO Read this register to determine if Debug features are on. This register returns 1 if reads to other registers designated as RW return the last value the IP writes to the register.
0x0010 CONSTANT_ALPHA RO RO Read this register to determine if the chroma key is operating in the constant alpha mode.
0x0014 CONSTANT_ALPHA_TAG RO RO Read this register for the value of alpha appended to pixels when operating in the constant alpha mode.
0x0018 BITS_PER_SYMBOL RO RO Read this register for the number of bits that represent each color plane.
0x001C NUM_COLOR_PLANES RO RO Read this register for the number of color planes.
0x0020 PIXELS_IN_PARALLEL RO RO Read this register for the number of pixels processed each clock cycle.
Control and debug registers

For more details about these registers, refer to Control Packets

0x0120 IMG_INFO_WIDTH RW RO

For lite variants, use this register to set the expected width of the incoming video fields.

For full variants, read this register for the received width the IP derives from the image information packets.

0x0124 IMG_INFO_HEIGHT RW RO

For lite variants, use this register to set the expected height of the incoming video fields.

For full variants, read this register for the received height the IP derives from the image information packets.

0x0128 IMG_INFO_INTERLACE RW RO

For lite variants, use this register to set the expected interlace information of the incoming video fields.

For full variants, read this register for the received interlace information the IP derives from the image information packets.

0x012C RESERVED RW RO Unused
0x0130 IMG_INFO_COLORSPACE RW RO

For lite variants, use this register to set the expected color space of the incoming video fields.

For full variants, read this register for the received color space the IP derives from the image information packets.

0x0134 IMG_INFO_SUBSAMPLING RW RO

For lite variants, use this register to set the expected chroma subsampling of the incoming video fields.

For full variants, read this register for the received chroma subsampling the IP derives from the image information packets.

0x0138 IMG_INFO_COSITING RW RO

For lite variants, use this register to set the expected chroma co-siting of theincoming video fields.

For full variants, read this register for the received chroma co-siting the IP derives from the image information packets.

0x013C IMG_INFO_FIELD_COUNT - RO The received field count field in image information packets.
0x0140 INPUT_STATUS RO RO

Bit 0: Status bit.

1 means Chroma Key is processing a video field, 0 otherwise.

When you turn off Lite mode:

Bit 1: Pending register updates bit.

Any writes to the output sampling register (0x0148) cause the IP to raise the pending register updates bit, to indicate outstanding changes to the chroma key settings. The IP lowers this bit at the next field boundary after a write to the COMMIT register.

0x0144 Commit - RW Only when you turn off lite mode. The IP holds any changes to the chroma key settings via the register map until you issue a write to this register. The value you write is unimportant.
0x0148 Matched_Alpha RW RW The alpha value appended to the pixels which meet the conditions specified using the upper and lower bounds registers.
0x014C Unmatched_Alpha RW RW The alpha value appended to the pixels which do not meet the conditions specified using the upper and lower bounds registers.
0x0150 C1_Upper_Bound RW RW The upper bound of the condition for the most significant color plane.
0x0154 C2_Upper_Bound RW RW The upper bound of the condition for the center color plane.
0x0158 C3_Upper_Bound RW RW

The upper bound of the condition for the least significant color plane.

This bound is for the condition for single color plane configurations.

0x015C C1_Lower_Bound RW RW The lower bound of the condition for the most significant color plane.
0x0160 C2_Lower_Bound RW RW The lower bound of the condition for the center color plane.
0x0164 C3_Lower_Bound RW RW

The lower bound of the condition for the least significant color plane.

This bound is for the condition for single color plane configurations.

0x0168 C1_Replace RW RW The replacement value for the most significant color plane if the pixel’s condition is met.
0x016C C2_Replace RW RW The replacement value for the center color plane if the pixel’s condition is met.
0x0170 C3_Replace RW RW

The replacement value for the least significant color plane if the pixel’s condition is met.

This bound is for the replacement of single color plane configurations.

0x0174 Compare_Enable RW RW

The control bits to enable or disable comparison of the color components when operating with conditional alpha and pixel replacement.

Bit 0: enables comparison of the most significant component (C1).

It is also the comparison bit for single color plane configurations

Bit 1: enables comparison of the middle component (C2).

Bit 2: enables comparison of the least significant component (C3).

0x0178 Replace_Enable RW RW

The control bits to enable or disable replacement of the color components when operating with conditional alpha and pixel replacement.

Bit 0: enables replacement of the most significant component (C1).

It is also the replacement field for single color plane configurations.

Bit 1: enables replacement of the middle component (C2).

Bit 2: enables replacement of the least significant component (C3).

Register Bit Descriptions

Table 84.   PROD_ID
Name Bits Description
Chroma Key product ID 31:0 This register always returns 0x6AF7_023F.
Table 85.  VER
Name Bits Description
Register map version 7:0 Register map version. Returns 0x01.
Unused 15:8 Unused. Returns 0x00
QPDS minor revision 23:16 Updated for each release. For 21.4, returns 0x04
QPDS major revision 31:24 Updated for each release. For 21.4, returns 0x15.
Table 86.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 0 Returns1 if you turn on lite mode.
Unused 31:1 Unused.
Table 87.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 0 Returns1 if you turn on Debug features.
Unused 31:1 Unused.
Table 88.  CONSTANT_ALPHA
Name Bits Description
Constant Alpha parameterization bit 0 Returns 1 if you turn on Constant Alpha.
Unused 31:1 Unused.
Table 89.  CONSTANT_ALPHA_TAG
Name Bits Description
Constant Alpha Tag Value 15:0 This register returns the constant value being appended to each pixel when Constant Alpha mode is on.
Unused 31:16 Unused.
Table 90.  BITS_PER_SYMBOL
Name Bits Description
BPS Value 31:0 This register returns the number of bits per color plane (symbol).
Table 91.  NUM_COLOR_PLANES
Name Bits Description
Number of Color Planes 31:0 This register returns the number of color planes you parameterize the IP for.
Table 92.  PIXELS_IN_PARALLEL
Name Bits Description
Pixels in Parallel 31:0 This register returns the number of pixels processed each clock cycle.
Table 93.  IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

When you turn on lite mode, write to this register to set the expected width of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the width-1 field from the most recently received image information packet and adds 1 to return a value for width.

unused 31:16 Unused.
Table 94.  IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

When you turn on lite mode, write to this register to set the expected height of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the height-1 field from the most recently received image information packet and adds 1 to return a value for height.

unused 31:16 Unused.
Table 95.  IMG_INFO_INTERLACE
Name Bits Description
InterlaceNibble bits 3:0

When you turn on lite mode, write to this register to set the expected interlacing of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the intlaceNibble field from the most recently received image information packet.

unused 31:4 Unused.
Table 96.  IMG_INFO_COLORSPACE
Name Bits Description
CSPcode bits 6:0

When you turn on lite mode, write to this register to set the expected color space of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the 7 bit CSP field from the most recently received image information packet.

unused 31:7 Unused.
Table 97.  IMG_INFO_SUBSAMPLING
Name Bits Description
CSPSubSacode bits 1:0

When you turn on lite mode, write to this register to set the expected chroma subsampling of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the SUBSA field from the most recently received image information packet.

unused 31:2 Unused.
Table 98.  IMG_INFO_COSITING
Name Bits Description
Cositecode bits 1:0

When you turn on lite mode, write to this register to set the expected chroma co-siting of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the COSITE field from the most recently received image information packet.

Unused 31:2 Unused
Table 99.  IMG_INFO_FIELD_COUNT
Name Bits Description
Countbits 6:0

When you turn on lite mode, this register has no function.

When you turn off lite mode and turn on Debug features, this register returns the 7 bit FIELD_COUNT field from the most recently received image information packet.

Unused 31:7 Unused
Table 100.  INPUT_STATUS
Name Bits Description
Status bit 0 1 means the chroma key is receiving and processing a video field, 0 otherwise.
Pending register updates bit 1 1 means the configurable chroma key registers have pending updates, 0 otherwise.
Unused 31:2 Unused
Table 101.  COMMIT
Name Bits Description
Commit 31:0 Write to any bits to trigger a commit.
Table 102.  MATCHED_ALPHA
Name Bits Description
Alpha Value 15:0 The alpha value appended to the pixels that meets the conditions specified using the upper and lower bounds registers.
Unused 31:16 Unused.
Table 103.  UNMATCHED_ALPHA
Name Bits Description
Alpha Value 15:0 The alpha value appended to the pixels that does not meet the conditions specified using the upper and lower bounds registers.
Unused 31:16 Unused.
Table 104.  C1_UPPER_BOUND
Name Bits Description
Upper Bound 15:0 The upper bound of the comparison range of the most significant color plane used in alpha matching and value replacement, if enabled.
Unused 31:16 Unused.
Table 105.   C2_UPPER_BOUND
Name Bits Description
Upper Bound 15:0 The upper bound of the comparison range of the center color plane used in alpha matching and value replacement, if enabled.
Unused 31:16 Unused.
Table 106.  C3_UPPER_BOUND
Name Bits Description
Upper Bound 15:0 The upper bound of the comparison range of the least significant color plane used in alpha matching and value replacement, if enabled.
Unused 31:16 Unused.
Table 107.  C1_LOWER_BOUND
Name Bits Description
Lower Bound 15:0 The lower bound of the comparison range of the most significant color plane used in alpha matching and value replacement, if enabled.
Unused 31:16 Unused.
Table 108.  C2_LOWER_BOUND
Name Bits Description
Lower Bound 15:0 The lower bound of the comparison range of the center color plane used in alpha matching and value replacement, if enabled.
Unused 31:16 Unused.
Table 109.  C3_LOWER_BOUND
Name Bits Description
Lower Bound 15:0 The lower bound of the comparison range of the least significant color plane used in alpha matching and value replacement, if enabled.
Unused 31:16 Unused.
Table 110.  C1_REPLACEMENT
Name Bits Description
Replacement 15:0 The replacement value of the most significant color plane if enabled and the pixel lays within the range.
Unused 31:16 Unused.
Table 111.  C2_REPLACEMENT
Name Bits Description
Replacement 15:0 The replacement value of the center color plane if enabled and the pixel lays within the range.
Unused 31:16 Unused.
Table 112.  C3_REPLACEMENT
Name Bits Description
Replacement 15:0 The replacement value of the least significant color plane if enabled and the pixel lays within the range.
Unused 31:16 Unused.
Table 113.  COMPARE_ENABLE
Name Bits Description
C1 Compare Enable 0 1= Enabled in pixel comparison, 0 = Disabled in pixel comparison.
C2 Compare Enable 1 1= Enabled in pixel comparison, 0 = Disabled in pixel comparison.
C3 Compare Enable 2 1= Enabled in pixel comparison, 0 = Disabled in pixel comparison.
Unused 31:3 Unused.
Table 114.  REPLACE_ENABLE
Name Bits Description
C1 Replace Enable 0 1= Enabled in color plane replacement, 0 = Disabled in color plane replacement.
C2 Replace Enable 1 1= Enabled in color plane replacement, 0 = Disabled in color plane replacement.
C3 Replace Enable 2 1= Enabled in color plane replacement, 0 = Disabled in color plane replacement.
Unused 31:3 Unused.
12

When you turn on lite mode, registers are RW only if you turn on Debug features, otherwise they are WO. For full, turn off lite mode.