Video and Vision Processing Suite Intel® FPGA IP User Guide

Download PDF
ID 683329
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Bits per Color Sample Adapter Intel FPGA IP x
10.1. About the Bits per Color Sample Adapter IP 10.2. Bits per Color Sample Adapter IP Parameters 10.3. Bits per Color Sample Adapter IP Interfaces 10.4. Bits per Color Sample Adapter IP Registers 10.5. Bits per Color Sample Adapter Software API
10.1. About the Bits per Color Sample Adapter IP x
10.1.1. Bits per Color Sample Adapter IP Performance and Resources
11. Chroma Key Intel® FPGA IP x
11.1. About the Chroma Key IP 11.2. Chroma Key IP Parameters 11.3. Chroma Key IP Interfaces 11.4. Chroma Key Replacement 11.5. Chroma Key IP Registers 11.6. Chroma Key IP Software API
11.1. About the Chroma Key IP x
11.1.1. Chroma Key IP Performance and Resources
12. Chroma Resampler Intel® FPGA IP x
12.1. About the Chroma Resampler IP 12.2. Chroma Resampler IP Parameters 12.3. Chroma Resampler IP Functional Description 12.4. Chroma Resampler IP Registers 12.5. Chroma Resampler IP Software API
12.1. About the Chroma Resampler IP x
12.1.1. Chroma Resampler Performance and Resources
12.3. Chroma Resampler IP Functional Description x
12.3.1. Chroma Resampler IP Interfaces
13. Clipper Intel® FPGA IP x
13.1. About the Clipper IP 13.2. Clipper IP Parameters 13.3. Clipper IP Interfaces 13.4. Clipper IP Registers 13.5. Clipper IP Software API
13.1. About the Clipper IP x
13.1.1. Clipper IP Performance and Resources
14. Clocked Video Input Intel® FPGA IP x
14.1. About the Clocked Video Input IP 14.2. Initializing the Clocked Video Input IP 14.3. Clocked Video Input IP Parameters 14.4. Clocked Video Input IP Interfaces 14.5. Clocked Video Input IP Registers 14.6. Clocked Video Input IP Software API
14.1. About the Clocked Video Input IP x
14.1.1. Clocked Video Input IP Features 14.1.2. Clocked Video Input IP Performance and Resources
15. Clocked Video to Full-Raster Converter Intel® FPGA IP x
15.1. About the Clocked Video to Full-Raster Converter IP 15.2. Clocked Video to Full-Raster Converter Parameters 15.3. Clocked Video to Full-Raster Converter Block Description 15.4. Clocked Video Converter to Full-Raster IP Registers
15.1. About the Clocked Video to Full-Raster Converter IP x
15.1.1. Clocked Video to Full-Raster Converter Features 15.1.2. Clocked Video to Full-Raster Converter Performance and Resources
15.3. Clocked Video to Full-Raster Converter Block Description x
15.3.1. Clocked Video to Full-Raster Converter Interfaces
16. Clocked Video Output Intel® FPGA IP x
16.1. About the Clocked Video Output IP 16.2. Clocked Video Output IP Parameters 16.3. Clocked Video Output IP Functional Description 16.4. Clocked Video Output IP Interfaces 16.5. Clocked Video Output IP Registers 16.6. Clocked Video Output IP Software API
16.1. About the Clocked Video Output IP x
16.1.1. Clocked Video Output IP Performance and Resources 16.1.2. Clocked Video Output IP Features
17. Color Space Converter Intel® FPGA IP x
17.1. About the Color Space Converter IP 17.2. Color Space Converter IP Parameters 17.3. Color Space Converter IP Functional Description 17.4. Color Space Converter IP Registers 17.5. Color Space Converter IP Software API
17.1. About the Color Space Converter IP x
17.1.1. Color Space Converter IP Features 17.1.2. Color Space Converter IP Performance and Resources
17.3. Color Space Converter IP Functional Description x
17.3.1. Color Space Converter IP Interfaces
18. Deinterlacer Intel® FPGA IP x
18.1. About the Deinterlacer IP 18.2. Deinterlacer Parameters 18.3. Deinterlacer Interfaces 18.4. Deinterlacer IP Registers 18.5. Deinterlacer IP Software API
18.1. About the Deinterlacer IP x
18.1.1. Deinterlacer Performance and Resources
19. FIR Filter Intel® FPGA IP x
19.1. About the FIR Filter 19.2. FIR Filter Parameters 19.3. FIR Filter IP Operation 19.4. FIR Filter Interfaces 19.5. FIR Filter Registers 19.6. FIR Filter IP Software API
19.1. About the FIR Filter x
19.1.1. FIR Filter IP Performance and Resources
19.3. FIR Filter IP Operation x
19.3.1. FIR Filter Processing 19.3.2. FIR Filter Precision 19.3.3. FIR Coefficient Specification 19.3.4. FIR Filter Symmetry 19.3.5. Result to Output Data Type Conversion
19.3.4. FIR Filter Symmetry x
19.3.4.1. No Symmetry 19.3.4.2. Horizontal Symmetry 19.3.4.3. Vertical Symmetry 19.3.4.4. Horizontal and Vertical Symmetry 19.3.4.5. Diagonal Symmetry
20. Frame Cleaner Intel® FPGA IP x
20.1. About the Frame Cleaner IP 20.2. Frame Cleaner IP Parameters 20.3. Frame Cleaner IP Functional Description 20.4. Frame Cleaner IP Interfaces 20.5. Frame Cleaner IP Registers 20.6. Frame Cleaner IP Software API
20.1. About the Frame Cleaner IP x
20.1.1. Frame Cleaner IP Performance and Resources
21. Full-Raster to Clocked Video Converter Intel® FPGA IP x
21.1. About the Full-Raster to Clocked Video Converter 21.2. Full Raster to Clocked Video Converter Parameters 21.3. Full-Raster to Clocked Video Converter Block Description 21.4. Full-Raster to Clocked Video Converter Registers
21.1. About the Full-Raster to Clocked Video Converter x
21.1.1. Full-Raster to Clocked Video Converter Features 21.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
21.3. Full-Raster to Clocked Video Converter Block Description x
21.3.1. Full Raster to Clocked Video Converter Interfaces
22. Full-Raster to Streaming Converter Intel® FPGA IP x
22.1. About the Full-Raster to Streaming Converter IP 22.2. Full-Raster to Streaming Converter Parameters 22.3. Full-Raster to Streaming Converter Block Description
22.1. About the Full-Raster to Streaming Converter IP x
22.1.1. Full-Raster to Streaming Converter Features 22.1.2. Full-Raster to Streaming Converter Performance and Resources
22.3. Full-Raster to Streaming Converter Block Description x
22.3.1. Full-Raster to Streaming Converter Interfaces
23. Genlock Controller Intel® FPGA IP x
23.1. About the Genlock Controller IP 23.2. Genlock Controller IP Parameters 23.3. Genlock Controller IP Functional Description 23.4. Using Genlock Controller IP Software 23.5. Genlock Controller IP Registers 23.6. Genlock Controller IP Software API
23.1. About the Genlock Controller IP x
23.1.1. Genlock Controller IP Performance and Resources
23.3. Genlock Controller IP Functional Description x
23.3.1. Genlock Controller IP Interfaces
23.4. Using Genlock Controller IP Software x
23.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 23.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 23.4.3. Setting the VCXO hold over 23.4.4. Restarting the Genlock Controller IP 23.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 23.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 23.4.7. Disturbing a Reference Clock (a cable pull)
24. Generic Crosspoint Intel® FPGA IP x
24.1. About the Generic Crosspoint IP 24.2. Generic Crosspoint IP Parameters 24.3. Generic Crosspoint IP Interfaces 24.4. Generic Crosspoint IP Registers 24.5. Generic Crosspoint IP Software API
24.1. About the Generic Crosspoint IP x
24.1.1. Generic Crosspoint IP Features 24.1.2. Generic Crosspoint Performance and Resources
25. Genlock Signal Router Intel® FPGA IP x
25.1. About the Genlock Signal Router IP 25.2. Genlock Signal Router IP Parameters 25.3. Genlock Signal Router IP Interfaces 25.4. Genlock Signal Router IP Registers 25.5. Genlock Signal Router IP Software API
25.1. About the Genlock Signal Router IP x
25.1.1. Genlock Signal Router IP Features 25.1.2. Genlock Signal Router IP Performance and Resources
26. Guard Bands Intel® FPGA IP x
26.1. About the Guard Bands IP 26.2. Guard Bands IP Parameters 26.3. Guard Bands IP Interfaces 26.4. Guard Bands IP Registers 26.5. Guard Bands IP Software API
26.1. About the Guard Bands IP x
26.1.1. Guard Bands IP Performance and Resources
27. Interlacer Intel® FPGA IP x
27.1. About the Interlacer IP 27.2. Interlacer IP Parameters 27.3. Interlacer IP Functional Description 27.4. Interlacer IP Registers 27.5. Interlacer IP Software API
27.1. About the Interlacer IP x
27.1.1. Interlacer IP Performance and Resources
27.3. Interlacer IP Functional Description x
27.3.1. Interlacer IP Interfaces
28. Mixer Intel® FPGA IP x
28.1. About the Mixer IP 28.2. Mixer IP Parameters 28.3. Mixer IP Functional Description 28.4. Mixer IP Registers 28.5. Mixer IP Software API
28.1. About the Mixer IP x
28.1.1. Mixer IP Performance and Resources
28.3. Mixer IP Functional Description x
28.3.1. Mixer IP Interfaces
29. Pixels in Parallel Converter Intel® FPGA IP x
29.1. About the Pixels in Parallel Converter IP 29.2. Pixels in Parallel Converter IP Parameters 29.3. Pixels in Parallel Converter Interfaces 29.4. Pixels in Parallel Converter Registers 29.5. Pixels in Parallel Converter IP Software API
29.1. About the Pixels in Parallel Converter IP x
29.1.1. Pixels in Parallel Converter IP Performance and Resources
30. Scaler Intel® FPGA IP x
30.1. About the Scaler 30.2. Scaler IP Parameters 30.3. Scaler IP Functional Description 30.4. Scaler IP Registers 30.5. Scaler IP Software API
30.1. About the Scaler x
30.1.1. Scaler IP Performance and Resources
30.2. Scaler IP Parameters x
30.2.1. Scaler Maximum Resolution
30.3. Scaler IP Functional Description x
30.3.1. Coefficient Selection 30.3.2. Coefficient Quantization 30.3.3. Filter Behavior at Edge Boundaries 30.3.4. Partial Frame Scaling 30.3.5. 422 and 420 Chroma Sampled Data Scaling 30.3.6. Scaler IP Interfaces
30.3.1. Coefficient Selection x
30.3.1.1. Updating Scaler IP Runtime Coefficients
31. Stream Cleaner Intel® FPGA IP x
31.1. About the Stream Cleaner IP 31.2. Stream Cleaner IP Parameters 31.3. Stream Cleaner IP Functional Description
31.1. About the Stream Cleaner IP x
31.1.1. Stream Cleaner IP Performance and Resources
31.3. Stream Cleaner IP Functional Description x
31.3.1. Stream Cleaner IP Interfaces
32. Switch Intel® FPGA IP x
32.1. About the Switch IP 32.2. Switch IP Parameters 32.3. Switch IP Functional Description 32.4. Switch IP Registers 32.5. Switch IP Software API
32.1. About the Switch IP x
32.1.1. Switch IP Performance and Resources
32.3. Switch IP Functional Description x
32.3.1. Switch IP Latency 32.3.2. Switch IP Interfaces
33. Tone Mapping Operator Intel® FPGA IP x
33.1. About the Tone Mapping Operator IP 33.2. TMO IP Parameters 33.3. TMO IP Block Description 33.4. TMO IP Registers 33.5. TMO IP Software API
33.1. About the Tone Mapping Operator IP x
33.1.1. TMO IP Features 33.1.2. TMO IP Performance and Resource Utilization
33.3. TMO IP Block Description x
33.3.1. TMO IP Interfaces 33.3.2. TMO IP Latency
34. Test Pattern Generator Intel® FPGA IP x
34.1. About the Test Pattern Generator IP 34.2. Test Pattern Generator IP Parameters 34.3. Test Pattern Generator IP Functional Description 34.4. Test Pattern Generator IP Registers 34.5. Test Pattern Generator IP Software API
34.1. About the Test Pattern Generator IP x
34.1.1. Test Pattern Generator IP Performance and Resources
34.3. Test Pattern Generator IP Functional Description x
34.3.1. Test Pattern Generator IP Interfaces
35. Video and Vision Monitor Intel FPGA IP x
35.1. About the Video and Vision Monitor IP 35.2. Video and Vision Monitor IP Parameters 35.3. Video and Vision Monitor IP Functional Description 35.4. Video and Vision Monitor IP Registers 35.5. Video and Vision Monitor Software API
35.1. About the Video and Vision Monitor IP x
35.1.1. Video and Vision Monitor IP Performance and Resources
35.3. Video and Vision Monitor IP Functional Description x
35.3.1. Video and Vision Monitor IP Interfaces
36. Video Frame Buffer Intel® FPGA IP x
36.1. About the Video Frame Buffer IP 36.2. Video Frame Buffer IP Parameters 36.3. Video Frame Buffer IP Functional Description 36.4. Video Frame Buffer IP Registers 36.5. Video Frame Buffer IP Software API
36.1. About the Video Frame Buffer IP x
36.1.1. Video Frame Buffer Performance and Resources
36.3. Video Frame Buffer IP Functional Description x
36.3.1. Video Frame Buffer IP Interfaces
37. Video Frame Reader Intel FPGA IP x
37.1. About the Video Frame Reader IP 37.2. Video Frame Reader IP Parameters 37.3. Video Frame Reader IP Functional Description 37.4. Video Frame Reader IP Registers 37.5. Video Frame Reader IP Software API
37.1. About the Video Frame Reader IP x
37.1.1. Video Frame Reader IP Performance and Resources
37.3. Video Frame Reader IP Functional Description x
37.3.1. Video Frame Reader IP Interfaces
38. Video Frame Writer Intel FPGA IP x
38.1. About the Video Buffer Writer IP 38.2. Video Frame Writer IP Parameters 38.3. Video Frame Writer IP Functional Description 38.4. Video Frame Writer IP Registers 38.5. Video Frame Writer IP Software API
38.1. About the Video Buffer Writer IP x
38.1.1. Video Frame Writer IP Performance and Resources
38.3. Video Frame Writer IP Functional Description x
38.3.1. Video Frame Writer IP Interfaces
39. Video Streaming FIFO Intel® FPGA IP x
39.1. About the Video Streaming FIFO IP 39.2. Video Streaming FIFO IP Parameters 39.3. Video Streaming FIFO IP Interfaces
39.1. About the Video Streaming FIFO IP x
39.1.1. Video Streaming FIFO IP Performance and Resources
40. Video Timing Generator Intel® FPGA IP x
40.1. About the Video Timing Generator IP 40.2. Video Timing Generator IP Parameters 40.3. Video Timing Generator IP Functional Description 40.4. Video Timing Generator IP Interfaces 40.5. Video Timing Generator IP Registers 40.6. Video Timing Generator IP Software API
40.1. About the Video Timing Generator IP x
40.1.1. Video Timing Generator IP Features 40.1.2. Video Timing Generator IP Performance and Resources
41. Warp Intel® FPGA IP x
41.1. About the Warp IP 41.2. Warp IP Parameters 41.3. Warp IP Block Description 41.4. Warp IP Registers 41.5. Warp IP Software API
41.1. About the Warp IP x
41.1.1. Warp IP Features 41.1.2. Warp IP Performance and Resource Utilization
41.3. Warp IP Block Description x
41.3.1. Block Cache Tool 41.3.2. Warp IP Interfaces 41.3.3. Warp IP Latency 41.3.4. External Memory for Warp IP
41.5. Warp IP Software API x
41.5.1. Using Warp IP Software 41.5.2. Warp IP Software Code Examples
42. Design Security x
42.1. Memory Subsystems 42.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Bits per Color Sample Adapter Intel FPGA IP
11. Chroma Key Intel® FPGA IP
12. Chroma Resampler Intel® FPGA IP
13. Clipper Intel® FPGA IP
14. Clocked Video Input Intel® FPGA IP
15. Clocked Video to Full-Raster Converter Intel® FPGA IP
16. Clocked Video Output Intel® FPGA IP
17. Color Space Converter Intel® FPGA IP
18. Deinterlacer Intel® FPGA IP
19. FIR Filter Intel® FPGA IP
20. Frame Cleaner Intel® FPGA IP
21. Full-Raster to Clocked Video Converter Intel® FPGA IP
22. Full-Raster to Streaming Converter Intel® FPGA IP
23. Genlock Controller Intel® FPGA IP
24. Generic Crosspoint Intel® FPGA IP
25. Genlock Signal Router Intel® FPGA IP
26. Guard Bands Intel® FPGA IP
27. Interlacer Intel® FPGA IP
28. Mixer Intel® FPGA IP
29. Pixels in Parallel Converter Intel® FPGA IP
30. Scaler Intel® FPGA IP
31. Stream Cleaner Intel® FPGA IP
32. Switch Intel® FPGA IP
33. Tone Mapping Operator Intel® FPGA IP
34. Test Pattern Generator Intel® FPGA IP
35. Video and Vision Monitor Intel FPGA IP
36. Video Frame Buffer Intel® FPGA IP
37. Video Frame Reader Intel FPGA IP
38. Video Frame Writer Intel FPGA IP
39. Video Streaming FIFO Intel® FPGA IP
40. Video Timing Generator Intel® FPGA IP
41. Warp Intel® FPGA IP
42. Design Security
43. Document Revision History for Video and Vision Processing Suite User Guide

11.5. Chroma Key IP Registers

Each register is either read-only (RO) or read-write (RW).

In the software API the register names appear with a prefix of INTEL_VVP,INTEL_VVP_CORE, or INTEL_VVP_CHROMA_KEY as appropriate and with an optional REGsuffix.

Table 83.   Control Registers
Address Register Access Description
Lite 12 Full
Parameterization registers
0x0000 PROD_ID RO RO Read this register for the Chroma Key product ID. This register always returns 0x6AF7_023F.
0x0004 VER RO RO Read this register to retrieve the version information for the Chroma Key.
0x0008 LITE_MODE RO RO

Read this register to determine if Lite mode is on or off.

This register returns 0 when Lite mode is off and 1 when on.

0x000C DEBUG_ENABLED RO RO Read this register to determine if Debug features are on. This register returns 1 if reads to other registers designated as RW return the last value the IP writes to the register.
0x0010 CONSTANT_ALPHA RO RO Read this register to determine if the chroma key is operating in the constant alpha mode.
0x0014 CONSTANT_ALPHA_TAG RO RO Read this register for the value of alpha appended to pixels when operating in the constant alpha mode.
0x0018 BITS_PER_SYMBOL RO RO Read this register for the number of bits that represent each color plane.
0x001C NUM_COLOR_PLANES RO RO Read this register for the number of color planes.
0x0020 PIXELS_IN_PARALLEL RO RO Read this register for the number of pixels processed each clock cycle.
Control and debug registers

For more details about these registers, refer to Control Packets

0x0120 IMG_INFO_WIDTH RW RO

For lite variants, use this register to set the expected width of the incoming video fields.

For full variants, read this register for the received width the IP derives from the image information packets.

0x0124 IMG_INFO_HEIGHT RW RO

For lite variants, use this register to set the expected height of the incoming video fields.

For full variants, read this register for the received height the IP derives from the image information packets.

0x0128 IMG_INFO_INTERLACE RW RO

For lite variants, use this register to set the expected interlace information of the incoming video fields.

For full variants, read this register for the received interlace information the IP derives from the image information packets.

0x012C RESERVED RW RO Unused
0x0130 IMG_INFO_COLORSPACE RW RO

For lite variants, use this register to set the expected color space of the incoming video fields.

For full variants, read this register for the received color space the IP derives from the image information packets.

0x0134 IMG_INFO_SUBSAMPLING RW RO

For lite variants, use this register to set the expected chroma subsampling of the incoming video fields.

For full variants, read this register for the received chroma subsampling the IP derives from the image information packets.

0x0138 IMG_INFO_COSITING RW RO

For lite variants, use this register to set the expected chroma co-siting of theincoming video fields.

For full variants, read this register for the received chroma co-siting the IP derives from the image information packets.

0x013C IMG_INFO_FIELD_COUNT - RO The received field count field in image information packets.
0x0140 INPUT_STATUS RO RO

Bit 0: Status bit.

1 means Chroma Key is processing a video field, 0 otherwise.

When you turn off Lite mode:

Bit 1: Pending register updates bit.

Any writes to the output sampling register (0x0148) cause the IP to raise the pending register updates bit, to indicate outstanding changes to the chroma key settings. The IP lowers this bit at the next field boundary after a write to the COMMIT register.

0x0144 Commit - RW Only when you turn off lite mode. The IP holds any changes to the chroma key settings via the register map until you issue a write to this register. The value you write is unimportant.
0x0148 Matched_Alpha RW RW The alpha value appended to the pixels which meet the conditions specified using the upper and lower bounds registers.
0x014C Unmatched_Alpha RW RW The alpha value appended to the pixels which do not meet the conditions specified using the upper and lower bounds registers.
0x0150 C1_Upper_Bound RW RW The upper bound of the condition for the most significant color plane.
0x0154 C2_Upper_Bound RW RW The upper bound of the condition for the center color plane.
0x0158 C3_Upper_Bound RW RW

The upper bound of the condition for the least significant color plane.

This bound is for the condition for single color plane configurations.

0x015C C1_Lower_Bound RW RW The lower bound of the condition for the most significant color plane.
0x0160 C2_Lower_Bound RW RW The lower bound of the condition for the center color plane.
0x0164 C3_Lower_Bound RW RW

The lower bound of the condition for the least significant color plane.

This bound is for the condition for single color plane configurations.

0x0168 C1_Replace RW RW The replacement value for the most significant color plane if the pixel’s condition is met.
0x016C C2_Replace RW RW The replacement value for the center color plane if the pixel’s condition is met.
0x0170 C3_Replace RW RW

The replacement value for the least significant color plane if the pixel’s condition is met.

This bound is for the replacement of single color plane configurations.

0x0174 Compare_Enable RW RW

The control bits to enable or disable comparison of the color components when operating with conditional alpha and pixel replacement.

Bit 0: enables comparison of the most significant component (C1).

It is also the comparison bit for single color plane configurations

Bit 1: enables comparison of the middle component (C2).

Bit 2: enables comparison of the least significant component (C3).

0x0178 Replace_Enable RW RW

The control bits to enable or disable replacement of the color components when operating with conditional alpha and pixel replacement.

Bit 0: enables replacement of the most significant component (C1).

It is also the replacement field for single color plane configurations.

Bit 1: enables replacement of the middle component (C2).

Bit 2: enables replacement of the least significant component (C3).

Register Bit Descriptions

Table 84.   PROD_ID
Name Bits Description
Chroma Key product ID 31:0 This register always returns 0x6AF7_023F.
Table 85.  VER
Name Bits Description
Register map version 7:0 Register map version. Returns 0x01.
Unused 15:8 Unused. Returns 0x00
QPDS minor revision 23:16 Updated for each release. For 21.4, returns 0x04
QPDS major revision 31:24 Updated for each release. For 21.4, returns 0x15.
Table 86.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 0 Returns1 if you turn on lite mode.
Unused 31:1 Unused.
Table 87.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 0 Returns1 if you turn on Debug features.
Unused 31:1 Unused.
Table 88.  CONSTANT_ALPHA
Name Bits Description
Constant Alpha parameterization bit 0 Returns 1 if you turn on Constant Alpha.
Unused 31:1 Unused.
Table 89.  CONSTANT_ALPHA_TAG
Name Bits Description
Constant Alpha Tag Value 15:0 This register returns the constant value being appended to each pixel when Constant Alpha mode is on.
Unused 31:16 Unused.
Table 90.  BITS_PER_SYMBOL
Name Bits Description
BPS Value 31:0 This register returns the number of bits per color plane (symbol).
Table 91.  NUM_COLOR_PLANES
Name Bits Description
Number of Color Planes 31:0 This register returns the number of color planes you parameterize the IP for.
Table 92.  PIXELS_IN_PARALLEL
Name Bits Description
Pixels in Parallel 31:0 This register returns the number of pixels processed each clock cycle.
Table 93.  IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

When you turn on lite mode, write to this register to set the expected width of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the width-1 field from the most recently received image information packet and adds 1 to return a value for width.

unused 31:16 Unused.
Table 94.  IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

When you turn on lite mode, write to this register to set the expected height of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the height-1 field from the most recently received image information packet and adds 1 to return a value for height.

unused 31:16 Unused.
Table 95.  IMG_INFO_INTERLACE
Name Bits Description
InterlaceNibble bits 3:0

When you turn on lite mode, write to this register to set the expected interlacing of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the intlaceNibble field from the most recently received image information packet.

unused 31:4 Unused.
Table 96.  IMG_INFO_COLORSPACE
Name Bits Description
CSPcode bits 6:0

When you turn on lite mode, write to this register to set the expected color space of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the 7 bit CSP field from the most recently received image information packet.

unused 31:7 Unused.
Table 97.  IMG_INFO_SUBSAMPLING
Name Bits Description
CSPSubSacode bits 1:0

When you turn on lite mode, write to this register to set the expected chroma subsampling of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the SUBSA field from the most recently received image information packet.

unused 31:2 Unused.
Table 98.  IMG_INFO_COSITING
Name Bits Description
Cositecode bits 1:0

When you turn on lite mode, write to this register to set the expected chroma co-siting of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the COSITE field from the most recently received image information packet.

Unused 31:2 Unused
Table 99.  IMG_INFO_FIELD_COUNT
Name Bits Description
Countbits 6:0

When you turn on lite mode, this register has no function.

When you turn off lite mode and turn on Debug features, this register returns the 7 bit FIELD_COUNT field from the most recently received image information packet.

Unused 31:7 Unused
Table 100.  INPUT_STATUS
Name Bits Description
Status bit 0 1 means the chroma key is receiving and processing a video field, 0 otherwise.
Pending register updates bit 1 1 means the configurable chroma key registers have pending updates, 0 otherwise.
Unused 31:2 Unused
Table 101.  COMMIT
Name Bits Description
Commit 31:0 Write to any bits to trigger a commit.
Table 102.  MATCHED_ALPHA
Name Bits Description
Alpha Value 15:0 The alpha value appended to the pixels that meets the conditions specified using the upper and lower bounds registers.
Unused 31:16 Unused.
Table 103.  UNMATCHED_ALPHA
Name Bits Description
Alpha Value 15:0 The alpha value appended to the pixels that does not meet the conditions specified using the upper and lower bounds registers.
Unused 31:16 Unused.
Table 104.  C1_UPPER_BOUND
Name Bits Description
Upper Bound 15:0 The upper bound of the comparison range of the most significant color plane used in alpha matching and value replacement, if enabled.
Unused 31:16 Unused.
Table 105.   C2_UPPER_BOUND
Name Bits Description
Upper Bound 15:0 The upper bound of the comparison range of the center color plane used in alpha matching and value replacement, if enabled.
Unused 31:16 Unused.
Table 106.  C3_UPPER_BOUND
Name Bits Description
Upper Bound 15:0 The upper bound of the comparison range of the least significant color plane used in alpha matching and value replacement, if enabled.
Unused 31:16 Unused.
Table 107.  C1_LOWER_BOUND
Name Bits Description
Lower Bound 15:0 The lower bound of the comparison range of the most significant color plane used in alpha matching and value replacement, if enabled.
Unused 31:16 Unused.
Table 108.  C2_LOWER_BOUND
Name Bits Description
Lower Bound 15:0 The lower bound of the comparison range of the center color plane used in alpha matching and value replacement, if enabled.
Unused 31:16 Unused.
Table 109.  C3_LOWER_BOUND
Name Bits Description
Lower Bound 15:0 The lower bound of the comparison range of the least significant color plane used in alpha matching and value replacement, if enabled.
Unused 31:16 Unused.
Table 110.  C1_REPLACEMENT
Name Bits Description
Replacement 15:0 The replacement value of the most significant color plane if enabled and the pixel lays within the range.
Unused 31:16 Unused.
Table 111.  C2_REPLACEMENT
Name Bits Description
Replacement 15:0 The replacement value of the center color plane if enabled and the pixel lays within the range.
Unused 31:16 Unused.
Table 112.  C3_REPLACEMENT
Name Bits Description
Replacement 15:0 The replacement value of the least significant color plane if enabled and the pixel lays within the range.
Unused 31:16 Unused.
Table 113.  COMPARE_ENABLE
Name Bits Description
C1 Compare Enable 0 1= Enabled in pixel comparison, 0 = Disabled in pixel comparison.
C2 Compare Enable 1 1= Enabled in pixel comparison, 0 = Disabled in pixel comparison.
C3 Compare Enable 2 1= Enabled in pixel comparison, 0 = Disabled in pixel comparison.
Unused 31:3 Unused.
Table 114.  REPLACE_ENABLE
Name Bits Description
C1 Replace Enable 0 1= Enabled in color plane replacement, 0 = Disabled in color plane replacement.
C2 Replace Enable 1 1= Enabled in color plane replacement, 0 = Disabled in color plane replacement.
C3 Replace Enable 2 1= Enabled in color plane replacement, 0 = Disabled in color plane replacement.
Unused 31:3 Unused.
12

When you turn on lite mode, registers are RW only if you turn on Debug features, otherwise they are WO. For full, turn off lite mode.

Level Two Title