Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022

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Document Table of Contents SDC Commands

Table 49.  SDC Commands usage in the Intel® Quartus® Prime Fitter and Timing Analyzer These SDC descriptions provided are overview for DCFIFO use case. For the exact SDC details, refer to the Intel® Quartus® Prime Timing Analyzer chapter in the Intel® Quartus® Prime Pro Edition Handbook.
SDC Command Fitter Timing Analyzer Recommended Settings
set_max_skew 34 To constraint placement and routing of flops in the multi-bit CDC paths to meet the specified skew requirement among bits.

To analyze whether the specified skew requirement is fully met. Both clock and data paths are taken into consideration.

Set to less than 1 launch clock.


Similar to set_max_skew but without taking clock skews into considerations.

To ensure the crossing latency is bounded.

To analyze whether the specified net delay requirement is fully met. Clock paths are not taken into consideration.

This is currently set to be less than 1 latch clock. 35


To relax fitter effort by mimicking the set_false_path command but without overriding other SDCs. 36

To relax timing analysis for the setup/hold checks to not fail. 37

This is currently set to 100ns/-100ns for max/min. 38

34 It can have significant compilation time impact in older Quartus versions without Timing Analyzer 2.
35 For advanced users, you can fine-tune the value based on your design. For instance, if the designs are able to tolerate longer crossing latency (full and empty status will be delayed), this can be relaxed.
36 Without set_false_path (which has the highest precedence and may result in very long insertion delays), Fitter will attempt to meet the default setup/hold which is extremely over constraint.
37 Without set_false_path, the CDC paths will be analyzed for default setup/hold, which is extremely over constraint.
38 Expect an approximately 100 ns delay when you observe CDC paths compared to set_false_path.

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