4.4. Shift Register (RAM-based) Intel® FPGA IP
The Shift Register (RAM-based) Intel® FPGA IP is a parameterized shift register with taps. The taps provide data outputs from the shift register at certain points in the shift register chain. You can add additional logic that uses the output from these taps for further applications. The output tap feature of the IP is useful for applications such as the Linear Feedback Shift Register (LFSR) and Finite Impulse Response (FIR) filters.
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