Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4. Shift Register (RAM-based) Intel® FPGA IP

The Shift Register (RAM-based) Intel® FPGA IP contains features not found in a conventional shift register. Traditional shift registers implemented with standard flipflops use many logic cells for large shift registers. The Shift Register (RAM-based) Intel® FPGA IP is implemented in the device memory blocks, saving logic cells and routing resources. In a complicated design such as a digital signal processing (DSP) application that requires local data storage, it is more efficient to implement an Shift Register (RAM-based) Intel® FPGA IP as the shift register.

The Shift Register (RAM-based) Intel® FPGA IP is a parameterized shift register with taps. The taps provide data outputs from the shift register at certain points in the shift register chain. You can add additional logic that uses the output from these taps for further applications. The output tap feature of the IP is useful for applications such as the Linear Feedback Shift Register (LFSR) and Finite Impulse Response (FIR) filters.

Did you find the information on this page useful?

Characters remaining:

Feedback Message