Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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Document Table of Contents

7. Document Revision History for the Intel® Agilex™ Embedded Memory User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.04.25 21.1 Updated the description for True Dual Port Dual Clock Emulator topic.
2021.09.20 21.1
  • Updated the following topics:
    • Read/Write Clock
    • Input/Output Clock
  • Updated the description for Dual clock: use separate ‘input’ and ‘output’ clocks in Tables: RAM: 1-PORT Intel® FPGA IP Parameter Settings and RAM: 2-PORT Intel® FPGA IP Parameter Settings.
  • Updated the description in Reset Scheme for clarity.
2021.06.11 21.1
  • Updated the Byte Enable in Intel® Agilex™ Embedded Memory Blocks to state that the byte width for the byte enable signal may differ depending on your selected memory block in the embedded memory IP parameter editors.
2021.03.29 21.1
  • Updated the Intel® Agilex™ Embedded Memory IP References to include information about inferring memory functions from HDL code.
  • Updated the following tables:
    • Mixed Port Read-During-Write Output Behaviors
    • RAM: 2-PORT Intel® FPGA IP Parameter Settings
    • RAM: 2-PORT Intel® FPGA IP Parameter Settings
    • RAM: 4-PORT Intel® FPGA IP Parameter Settings
    • ROM: 1-PORT Intel® FPGA IP Parameter Settings
    • ROM: 2-PORT Intel® FPGA IP Parameter Settings
    • eSRAM Intel® Agilex™ FPGA IP Parameter Editor: General Tab
    • FIFO Intel® FPGA IP Parameter Settings
2021.01.08 20.4 Updated the data bits written in Table: Byte Enable Controls in ×40 Data Width (M20K).
2020.12.14 20.4
  • Added the Shift Register (RAM-based) Intel® FPGA IP section.
  • Added the Avoid Changing Clock Signals and Other Memory Signals Simultaneously topic to the Intel® Agilex™ Embedded Memory Design Considerations section.
  • Added eSRAM Intel® FPGA IP information in Table: Intel® Agilex™ Memory IPs.
  • Updated Figure: Mixed-Port Read-During-Write: New_a_old_b Mode.
  • Updated the On Chip Memory RAM and ROM Intel® FPGA IPs section.
  • Updated the descriptions for the following parameters in Table: RAM: 1-PORT Intel® FPGA IP Parameters:
    • Create an ‘aclr’ asynchronous clear for the registered ports
    • Create an ‘sclr’ synchronous clear for the registered ports
  • Updated the description for clock0 in Table: Interface Signals of the Intel® Agilex™ RAM and ROM Intel® FPGA IP Cores.
  • Updated the eSRAM Intel Agilex FPGA IP chapter:
    • Updated Figure: eSRAM Channel.
    • Updated Table: eSRAM Intel Agilex FPGA IP Release Information.
    • Updated the widths for p<port_number>_data and p<port_number>_q signals in Table:eSRAM Intel Agilex FPGA IP Input and Output Signals.
  • Updated the FIFO Intel® FPGA IP chapter:
    • Updated the footnotes for aclr (synchronize with read clock) mode in Table: Asynchronous Clear in DCFIFO.
    • Updated the description in the Gray-Code Counter Transfer at the Clock Domain Crossing topic of the FIFO section.
2019.12.09 19.3
  • Updated the eSRAM System Features section.
  • Updated Table: eSRAM Intel® Agilex™ FPGA IP Core Parameter Editor: Port Tab:
    • Updated the description for How wide should the data bus be?.
    • Removed Enable Dynamic ECC Encoder and Decoder Bypass.
  • Updated the eSRAM Intel® Agilex™ FPGA IP Interface Signals section:
    • Updated the descriptions for p<port_number>_data and p<port_number>_q signals.
    • Removed p<port_number>_eccdecbypass and p<port_number>_eccencbypass.
2019.11.19 19.3
  • Updated Table: Mixed Port Read-During-Write Output Behaviors:
    • Updated the Output Data when Read-During-Write value of the constrained_dont_care and dont_care parameters from "New data" to "Don't care".
    • Added a footnote to state that the output data is "don't care" because the IP does not guarantee metastability for the output data when read-during-write.
  • Updated the FIFO Intel® FPGA IP section.
2019.10.25 19.3
  • Added Intel® Agilex™ Embedded Memory IP Core References chapter.
  • Added IP release information for:
    • RAM: 1-PORT Intel® FPGA IP version 19.2.0
    • RAM: 2-PORT Intel® FPGA IP version 19.2.0
    • RAM: 4-PORT Intel® FPGA IP version 19.2.0
    • ROM: 1-PORT Intel® FPGA IP version 19.2.0
    • ROM: 2-PORT Intel® FPGA IP version 19.2.0
    • eSRAM Intel® Agilex™ FPGA IP version 19.1.2
    • FIFO Intel® FPGA IP version 19.1
  • Added new Topics:
    • Intel® Agilex™ Supported Embedded Memory IP Cores
    • Timing/Power Optimization Feature in M20K Blocks
    • Avoid Providing Non-Deterministic Input
  • Updated the following topics:
    • Intel Agilex Embedded Memory Features
    • Force-to-Zero
    • Freeze Logic
    • True Dual Port Dual Clock Emulator
    • Mixed-Port Read-During-Write Mode
  • Updated the features for eSRAM memory blocks in Table: Intel Agilex Embedded Memory Features.
  • Updated the depth of the eSRAM memory blocks in Table: Supported Embedded Memory Block Configurations.
  • Updated the description for Don't Care output mode in Table: Output Modes for RAM in Mixed-Port Read-During-Write Mode.
  • Added eSRAM output register and power-up value in Table: Initial Power-Up Values of Embedded Memory Blocks.
Document Version Changes
2019.04.02 Initial release.

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