Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores

Table 17.  On Chip Memory RAM and ROM Intel® FPGA IP Cores Descriptions
On Chip Memory Intel® FPGA IP Cores Features
RAM: 1-PORT Intel® FPGA IP
  • Read and write operations from a single address.
  • Read enable port to specify the behavior of the RAM output ports during a write operation, to overwrite or retain existing value.
  • Emulates single-port RAM using DUAL_PORT configuration for block RAM.
RAM: 2-PORT Intel® FPGA IP

Simple dual-port RAM

  • One read and one write operations to different locations.
  • Supports error correction code (ECC).

True dual-port RAM

  • Two reads.
  • Two writes.
  • One read and one write at two different clock frequencies.
RAM: 4-PORT Intel® FPGA IP
  • Two reads and two writes to different locations.
ROM: 1-PORT Intel® FPGA IP
  • One port for read-only operations.
  • Emulates single-port ROM using DUAL_PORT configuration for block RAM.
ROM: 2-PORT Intel® FPGA IP
  • Two ports for read-only operations.
  • Emulates dual-port ROM using BIDIR_DUAL_PORT configuration for block RAM.

Did you find the information on this page useful?

Characters remaining:

Feedback Message