Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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2.8. Coherent Read Memory

The coherent read memory feature allows you to read out the output data that will be written into the same memory content in a single clock cycle. In other words, you will experience the new data (flow through) behavior during the read-during-write operation. This feature is applicable only for M20K blocks and supported only in single clock configuration.

If the M20K blocks are configured with coherent read memory feature enabled with registered output and Force-to-Zero feature disabled, the output register data will be held through the coherent read circuitry when the read enable (rden) signal is low (refer to Figure 9 and Figure 10 for more details). This circuitry behaves like a loop instead of fetching data from the latch of the M20K blocks. When asynchronous clear (aclr) or synchronous clear (sclr) is asserted to clear the output register of M20K blocks, the output remains as 0 until the next clock cycle, after the rden signal is asserted again.

Figure 9. Coherent Read Memory Behavior for Intel® Agilex™ BlocksThis figure shows an example of the coherent read memory behavior when coherent read memory feature is enabled with registered output and Force-To-Zero feature is disabled if the M20K blocks does not read when the clear signal is asserted high.
If you engage the coherent read memory feature, you cannot use the following configurations:
  • Operating modes other than simple dual-port
  • Simple dual-port with different port width
  • Byte enable
  • ECC
  • Wide simple dual-port
  • Dual clock configuration
Figure 10. Simplified Block Diagram of Coherent Read Memory Circuitry
Figure 11. Coherent Read Memory Behavior for Unregistered OutputThis figure shows the waveform of the coherent read memory when the output is unregistered.
Figure 12. Coherent Read Memory Behavior for Registered OutputThis figure shows the waveform of the coherent read memory when the output is registered.

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