Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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4.3.11.1. Embedded Timing Constraint

When using the Intel® Quartus® Prime Timing Analyzer with a design that contains a DCFIFO block apply the following false paths to avoid timing failures in the synchronization registers:
  • For paths crossing from the write into the read domain, apply a false path assignment between the delayed_wrptr_g and rs_dgwp registers:

    set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g[*]}] -to [get_registers {*dcfifo*rs_dgwp*}]

  • For paths crossing from the read into the write domain, apply a false path assignment between the rdptr_g and ws_dgrp registers:

    set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] -to [get_registers {*dcfifo*ws_dgrp*}]

The false path assignments are automatically added through the HDL-embedded Synopsis design constraint (SDC) commands when you compile your design. The related message is shown under the Timing Analyzer report.

Note: The constraints are internally applied but are not written to the Synopsis Design Constraint File (.sdc). To view the embedded-false path, type report_sdc in the console pane of the Timing Analyzer GUI.

If you use the Intel® Quartus® Prime Timing Analyzer, the false paths are applied automatically for the DCFIFO.

Note: If the DCFIFO is implemented in ALMs, you can ignore the cross-domain timing violations from the data path of the DFFE array (that makes up the memory block) to the q output register. To ensure the q output is valid, sample the output only after the rdempty signal is deasserted.

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