Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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2.3. Asynchronous Clear and Synchronous Clear

The Intel® Agilex™ M20K and MLAB embedded memory blocks support asynchronous clear and synchronous clear on output latches and output registers.
Note: The M20K blocks support asynchronous clear on read address registers, but is limited only to simple dual-port and simple quad-port modes. If the read address registers are cleared, M20K will read the memory content at address 0.

For the asynchronous clear (aclr) signal, the RAM outputs are cleared immediately when the aclr signal asserts. The outputs stay cleared until the next read cycle after the aclr signal de-asserts.

For the synchronous clear (sclr) signal, the RAM outputs are cleared at the next rising edge of the output clock when the (sclr) signal is asserted. The outputs will stay cleared until the next read cycle after the sclr signal de-asserts.

Note: Both aclr and sclr signals must be used separately for each RAM configuration.
Figure 5. Behavior of Asynchronous Clear and Synchronous Clear in Registered Mode
Figure 6. Behavior for Asynchronous Clear and Synchronous Clear in Unregistered Mode
Figure 7. Behavior When Asynchronous Clear is Used on Read Address Register in Registered and Unregistered Modes

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