Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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4.3.2. Configuration Methods

Table 37.  Configuration MethodsYou can configure and build the FIFO Intel® FPGA IP core with methods shown in the following table.
Method Description
Using the FIFO parameter editor. Intel® recommends using this method to build your FIFO Intel® FPGA IP core. It is an efficient way to configure and build the FIFO Intel® FPGA IP core. The FIFO parameter editor provides options that you can easily use to configure the FIFO Intel® FPGA IP core.

You can access the FIFO Intel® FPGA IP core parameter editor in Basic Functions > On Chip Memory > FIFO of the IP catalog.10

Manually instantiating the FIFO Intel® FPGA IP core. Use this method only if you are an expert user. This method requires that you know the detailed specifications of the IP core. You must ensure that the input and output ports used, and the parameter values assigned are valid for the FIFO Intel® FPGA IP core you instantiate for your target device.
10 Do not use dcfifo or scfifo as the entity name for your FIFO Platform Designer system.

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