Intel® Agilex™ Embedded Memory User Guide

ID 683241
Date 4/25/2022
Public

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4.3.6. FIFO Output Status Flag and Latency

The main concern in most FIFO design is the output latency of the read and write status signals.
Table 41.  Output Latency of the Status Flags for SCFIFOThis table shows the output latency of the write signal (wrreq) and read signal (rdreq) for the SCFIFO according to the different output modes and optimization options.
Output Mode Optimization Option 20 Output Latency (in number of clock cycles)
Normal 21 Speed wrreq / rdreq to full: 1
wrreq to empty: 2
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
rdreq to q[]: 1
Area wrreq / rdreq to full: 1
wrreq / rdreq to empty : 1
wrreq / rdreq to usedw[] : 1
rdreq to q[]: 1
Show-ahead 21 Speed wrreq / rdreq to full: 1
wrreq to empty: 3
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
wrreq to q[]: 3
rdreq to q[]: 1
Area wrreq / rdreq to full: 1
wrreq to empty: 2
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
wrreq to q[]: 2
rdreq to q[]: 1
Table 42.  ALM Implemented RAM Mode for SCFIFO and DCFIFO
Output Mode Optimization Option 22 Output Latency (in number of clock cycles)
Normal 23 Speed wrreq / rdreq to full: 1
wrreq to empty: 1
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
rdreq to q[]: 1
Area wrreq / rdreq to full: 1
wrreq / rdreq to empty : 1
wrreq / rdreq to usedw[] : 1
rdreq to q[]: 1
Show-ahead 23 Speed wrreq / rdreq to full: 1
wrreq to empty: 1
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
wrreq to q[]: 1
rdreq to q[]: 1
Area wrreq / rdreq to full: 1
wrreq to empty: 1
rdreq to empty: 1
wrreq / rdreq to usedw[]: 1
wrreq to q[]: 1
rdreq to q[]: 1
Table 43.  Output Latency of the Status Flag for the DCFIFO This table shows the output latency of the write signal (wrreq) and read signal (rdreq) for the DCFIFO.
Output Latency (in number of clock cycles)
wrreq to wrfull: 1 wrclk
wrreq to rdfull: 2 wrclk cycles + following n rdclk 24
wrreq to wrempty: 1 wrclk
wrreq to rdempty: 2 wrclk 25 + following n rdclk 25
wrreq to wrusedw[]: 2 wrclk
wrreq to rdusedw[]: 2 wrclk + following n + 1 rdclk 25
wrreq to q[]: 1 wrclk + following 1 rdclk 25
rdreq to rdempty: 1 rdclk
rdreq to wrempty: 1 rdclk + following n wrclk 25
rdreq to rfull: 1 rdclk
rdreq to wrfull: 1 rdclk + following n wrclk 25
rdreq to rdusedw[]: 2 rdclk
rdreq to wrusedw[]: 1 rdclk + following n + 1 wrclk 25
rdreq to q[]: 1 rdclk
20 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON. Setting the parameter to OFF is equivalent to area optimization.
21 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode, the parameter is set to ON.
22 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON. Setting the parameter to OFF is equivalent to area optimization.
23 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode, the parameter is set to ON.
24 The number of n cycles for rdclk and wrclk is equivalent to the number of synchronization stages and are related to the WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE parameters. For more information about how the actual synchronization stage (n) is related to the parameters set for different target device, refer to FIFO Metastability Protection and Related Options .
25 This is applied only to Show-ahead output modes. Show-ahead output mode is equivalent to setting the LPM_SHOWAHEAD parameter to ON.

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